Abstract
Current rapid synthesis approaches for reusable dedicated hardware components (cores) for digital signal processing systems are ineffective since they fail to capture and exploit the manner in which the resulting components are used as part of a heterogeneous system. This leads to counter-productive core redesign for each use of the core. This paper presents a solution to this issue which combines a novel but intuitive system modeling technique and associated core generation and integration methodology which generates reuable core architectures which may be optimised via algorithm level transformations. For an example design problem, these provide an effective rapid core synthesis and implementation exploration flow which allows a factor 3.9 throughput increase with no extra hardware expense.
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S. Sriram and S. S. Bhattacharyya, Embedded Multiprocessors Scheduling and Synchronization, Marcel Dekker, Inc., New York, Basel, 2000.
B. K. Madahar, et al., “How Rapid is Rapid Prototyping? Analysis of ESPADON Programme Results,” EURASIP Journal on Applied Signal Processing, vol. 6, 2003, pp. 580–593.
J. McAllister, R. Woods, R. Walke, and D. Reilly, “Synthesis and High Level Optimisation of Multidimensional Dataflow Actor Networks on FPGA,” in Proc. IEEE W/shop on Sig. Proc. Sys., Texas, USA, 2004, pp. 164–169.
R. Lauwereins, M. Engels, M. Adé and J. A. Peperstraete, “Grape-II: A System-Level Prototyping Environment for DSP Applications,” IEEE Computer, Computer, 1995, pp. 35–43.
C. Hylands et al., “Overview of the Ptolemy Project,” Technical Memorandum UCB/ERL M03/25, University of California at Berkeley, 2003.
The CAP Laboratory of Seoul National University, “Peace Users Manualv.1.0b,” (available from http://peace.snu.ac.kr), 25, 2004.
T. Stefanov et al., “System Design using Kahn Process Networks: The Compaan/Laura Approach,” Proc. Design Automation and Test in Europe (DATE) Conference, vol.1, Paris, 2004 pp. 340–345.
E. A. Lee and T. M. Parks, “Dataflow Process Networks,” Proc. IEEE, vol. 83, no. 5, 1995, pp. 773–799.
S. S. Bhattacharyya, P. K. Murthy and E. A. Lee, Software Synthesis from Dataflow Graphs, Kluwer Academic Publishers, 1996.
E. A. Lee and D. G. Messerschmitt, “Synchronous Data Flow,” Proc. IEEE, vol. 75, no. 9, 1987, pp. 1235–1245.
E. A. Lee, “Consistency in Dataflow Graphs,” IEEE Trans. Parallel and Distributed Systems, vol. 2, no. 2, 1991, pp. 223–235.
P. K. Murthy and E. A. Lee, “Multidimensional Synchronous Dataflow,” IEEE Trans. Signal Processing, vol. 50, no. 8, 2002, pp. 2064–2079.
M. C. Williamson and E. A. Lee, “Synthesis of Parallel Hardware Implementations from Synchronous Dataflow Graph Specifications,” in Proc. 30th Asilomar Conference on Systems, Signals and Computers, vol. 2, USA, 1996, pp. 1340– 1343.
J. Dalcolmo, R. Lauwereins and M. Adé, “Code Generation of Data Dominated DSP Applications for FPGA Targets,” in Proc. 9th International Workshop on Rapid System Prototyping, Belgium, 1998 pp. 162–167.
H. Jung and S. Ha, “Hardware Synthesis from Coarse-Grained Dataflow Specification for Fast HW/SW Cosynthesis,” in Proc. International Conference on Hardware/Software Codesign and System Synthesis Sweden, 2004, pp. 24–29.
T. Harriss, R. Walke, B. Kienhuis and E. F. Deprettere, “Compilation from Matlab to Process Networks Realised in FPGA,” Design Automation for Embedded Systems, vol. 7, no. 4, 2002, pp. 385–403.
K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley & Sons, Inc., 1999.
Y. Yi, R. Woods, L. K. Ting and C. F. N. Cowan, “High Speed FPGA-based Implementations of Delayed-LMS Filters,” Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, vol. 39, nos. 1–2, 2005, pp. 113– 131.
Xilinx Inc., Virtex-II ProTM Platform FPGA Handbook, 2002.
D. J. Kaplan and R. S. Stevens, “Processing Graph Method 2.1 Semantics,” available at http://www.ait.nrl.navy.mil/pgmt_home.html, 29, 2002.
G. Bilsen, M. Engels, R. Lauwereins and J. Peperstraete, “Cyclo-Static Dataflow,” IEEE. Trans. Signal Processing, vol. 44, no. 2, 1996, pp. 397–408.
I. Cimpian et al, “Communication optimization in Compaan Process Networks,” in Proc. 4th Int. Workshop on Systems, Architectures, Modeling and Simulation (SAMOS), Samos, Greece, 2004, pp. 494–506.
O. Bringmann and W. Rosenstiel, “Resource Sharing in Hierarchical Synthesis,” in Proc. 1997 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), California, USA, 1997, pp. 318–325.
Y. Yi, R. Woods and J. V. McCanny, “Hierarchical Synthesis of Complex DSP Functions on FPGAs,” in Proc. 37th Asilomar Conference on Signals, Systems and Computers California, USA, 2003, pp. 1421–1426.
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John McAllister received a first honours B.Eng degree in Electrical and Electronic Engineering and the degree of PhD from Queen’s University Belfast, UK in 2001 and 2004 respectively.From October 2004 to July 2005 he was a Postdoctoral Research Assistant in the Programmable Systems Laboratory in the System on Chip research group in the Institute for Electronics, Communication and Information Technology (ECIT) at Queen’s University Belfast.In July 2005 he was appointed to a lectureship in SoC technology in the International Centre for System-on-Chip and Advanced Microwireless (SoCAM) project at ECIT.
Roger Woods received the degree of B.Sc with Honours in Electrical and Electronic Engineering and degree of Ph.D. from the Queen’s University of Belfast, UK in 1985 and 1990 respectively. From 2003, he has been a Professor at the same university and leads the programmable systems and networks laboratory there. His main research interests are programmable hardware systems using FPGAs, design tools for heterogeneous platforms and low power VLSI. He has published over 120 papers in the area of VLSI and DSP, holds two patents and serves on numerous technical program committees including Workshop on Signal Processing Systems, Field Programmable Logic and Field Programmable Technology. He is a member the IEEE Signal Processing Society Technical Committee for the Design and Implementation of Signal Processing Systems and chair of the IEE Professional Network on Microelectronics and Embedded Systems.
Richard Walke received his Ph.D. from Warwick University in 1998 for work on arithmetic, architectures and implementations of adaptive weight calculation in ASIC. Subsequently he worked on the implementation of a range of DSP algorithms in FPGA, specialising in floating-point arithmetic, digital receivers and adaptive beamformers on FPGA. In recent years he has lead work to address the design of heterogeneous systems employing both processor and FPGA. Last year he moved to Xilinx, and is now responsible for the development of their floating-point IP solution.
Darren Reilly received first honours B.Eng. Degree in Electronic and Software Engineering from the Queen’s University Belfast in 2002. He is currently pursuing a Ph.D. in Queen’s University Belfast due to finish in September 2005. His research interests lie in the rapid development of efficient architectures for FPGA as part of a system level design flow.
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Mcallister, J., Woods, R., Walke, R. et al. Multidimensional DSP Core Synthesis for FPGA. J VLSI Sign Process Syst Sign Image Video Technol 43, 207–221 (2006). https://doi.org/10.1007/s11265-006-7271-5
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DOI: https://doi.org/10.1007/s11265-006-7271-5