Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content

Still Image Processing on Coarse-Grained Reconfigurable Array Architectures

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recently coarse-grained reconfigurable array architectures (CGRAs), such as the ADRES CGRA and its corresponding DRESC compiler are gaining more popularity due to several technological breakthroughs in this area. We investigate the mapping of two image processing algorithms, Wavelet encoding and decoding, and TIFF compression on this novel type of array architectures in a systematic way. The results of our experiments show that CGRAs based on ADRES and its DRESC compiler technology deliver improved performance levels for these two benchmark applications when compared to results obtained on a state-of-the-art commercial DSP platform, the c64x DSP from Texas Instruments. ADRES/DRESC can beat its performance by at least 50% in cycle count and the power consumption even drops to 10% of the published numbers of the c64x DSP.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8

Similar content being viewed by others

References

  1. Bouwens, F. (2006). Power and performance optimization for adres. Master’s thesis, Delft University of Technology, The Netherlands, August.

  2. Hartenstein, R. (2001). A decade of reconfigurable computing: A visionary retrospective. In Proceedings of the conference on design, automation and test in Europe.

  3. Hiers, T., & Webster, M. (2008). Tms320c6414t/15t/16t power consumption summary. TI Document SPRAA45A, February.

  4. Cadence Design Systems Inc. (2008). Cadence Design Systems Inc. homepage. http://www.cadence.com.

  5. Chang, P. P., Mahlke, S. A., Chen, W. Y., & Wart, N. J. (1991). IMPACT: An architectural framework for multiple-instruction-issue process. SIGARCH Computer Architecture News, 19(3), 266–275.

    Article  Google Scholar 

  6. MiBench Benchmark Suite (2008). MiBench homepage. http://www.eecs.umich.edu/mibench.

  7. Mentor Graphics Corp. (2008). Mentor Graphics Corp. homepage. http://www.mentor.com.

  8. Synopsys Inc. (2008). Synopsys Inc. homepage. http://www.synopsys.com.

  9. Texas Instruments Inc. (2008). Texas Instruments Inc. homepage. http://www.ti.com.

  10. Kumar, M., Ganesan, A., Singh, S. May, F., & Becker J. (2007). H.264 decoder at HD resolution on a coarse grain dynamically reconfigurable architecture. In 17th international conference on field programmable logic and applications.

  11. Major, A., Nousias, I., Khawam, S., Milward, M., Yi, Y., & Arslan, T. (2007). H.264/AVC in-loop de-blocking filter targeting a dynamically reconfigurable instruction cell based architecture. In 17th international conference on field programmable logic and applications.

  12. Mei, B., Veredas, F.-J., & Masschelein, B. (2005). Mapping an H.264/AVC decoder onto the ADRES reconfigurable architecture. In Field programmable logic and applications, 2005. International conference (pp. 622–625), August.

  13. Mei, B., Vernalde, S., Verkest, D., De Man, H., & Lauwereins, R. (2003). ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. In Proc. of field-programmable logic and applications (pp. 61–70).

  14. Mei, B., Vernalde, S., Verkest, D., De Man, H., & Lauwereins, R. (2003). Exploiting loop-level parallelism for coarse-grained reconfigurable architecture using modulo scheduling. IEEE Proceedings. Computers and Digital Techniques, 150(5), 255–261, September.

    Article  Google Scholar 

  15. Nishimura, T., Hirai, K., Saito, Y., Nakamura, T., Hasegawa, Y., Tsutsusmi, S., et al. (2008). Power reduction techniques for dynamically reconfigurable processor arrays. In Field programmable logic and applications 2008, (pp. 305–310).

  16. Novo, D., Moffat, W., Derudder, V., & Bougard, B. (2005). Mapping a multiple antenna sdm-ofdm receiver on the adres coarse-grained reconfigurable processor. In Signal processing systems design and implementation, IEEE Workshop (pp. 473–478), November.

  17. Singh, H., Lee, M.-H., Lu, G., Kurdahi, F. J., & Bagherzadeh, N. (2000). Morphosys: An integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Transactions on Computers, 49, 465–481, May.

    Article  Google Scholar 

  18. Skodras, A., Christopoulos, C., & Ebrahimi, T. (2001). The JPEG2000 still image compression standard. IEEE Signal Processing Magazine, 9(7), 36–58, September.

    Article  Google Scholar 

Download references

Acknowledgements

The authors would like to thank Bjorn de Sutter and Bingfeng Mei for their input to this paper.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Matthias Hartmann.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Hartmann, M., Pantazis, V.(., Vander Aa, T. et al. Still Image Processing on Coarse-Grained Reconfigurable Array Architectures. J Sign Process Syst 60, 225–237 (2010). https://doi.org/10.1007/s11265-008-0309-0

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-008-0309-0

Keywords