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Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications

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An Erratum to this article was published on 28 February 2012

Abstract

This paper proposes a high-speed and area-efficient three-parallel Reed-Solomon (RS) decoder using the simplified degree computationless modified Euclid (S-DCME) algorithm for the key equation solver (KES) block. To achieve a high throughput rate, the inner signals, such as the syndrome, error locator and error value polynomials, are computed in parallel. In addition, the key equations are solved by using the S-DCME algorithm to reduce the hardware complexity. To handle the many problems caused by applying the S-DCME algorithm to the KES block, we modify the architectures of some of the blocks in the three-parallel RS decoder. The proposed RS architecture can reduce the hardware complexity by about 80% with respect to the KES block. In addition, the proposed RS architecture has an approximately 25% shorter latency than the conventional parallel RS architectures.

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Acknowledgments

This work was supported in part by the IT R&D program of MKE/KEIT [KI002145, High Speed Digital Signal Processing based CMOS Circuit Design for Next-generation Optical Communication] and in part by IDEC (IC Design Education Center).

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Authors and Affiliations

  1. School of Electronics and Computer Engineering, Ajou University, San 5, Wonchun-Dong, Yeungtong-Gu, 443-779, Suwon, Korea

    Jae Do Lee & Myung Hoon Sunwoo

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  1. Jae Do Lee
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  2. Myung Hoon Sunwoo
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Correspondence to Myung Hoon Sunwoo.

Additional information

An erratum to this article can be found at http://dx.doi.org/10.1007/s11265-012-0659-5.

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Lee, J.D., Sunwoo, M.H. Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications. J Sign Process Syst 66, 15–24 (2012). https://doi.org/10.1007/s11265-010-0517-2

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  • DOI: https://doi.org/10.1007/s11265-010-0517-2

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