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Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems

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Abstract

Designing accelerators for the real-time computation of Fast Fourier Transform (FFT) algorithms for state-of-the-art Orthogonal Frequency-Division Multiplexing (OFDM) demodulators has always been challenging. We have scaled-up a template-based Coarse-Grain Reconfigurable Array device for faster FFT processing that generates special purpose accelerators based on the user input. Using a basic and a scaled-up version, we have generated a radix-4 and mixed-radix (2, 4) FFT accelerator to process different length and types of algorithms. Our implementation results show that these accelerators satisfy not only the execution time requirements of FFT processing for Single Input Single Output (SISO) wireless standards that are IEEE-802.11 a/g and 3GPP-LTE but also for Multiple Input Multiple Output (MIMO) IEEE-802.11n standard.

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References

  1. Brunelli, C., Garzia, F., & Nurmi, J. (2008). A Coarse-Grain Reconfigurable Architecture for Multimedia Applications Featuring Subword Computation Capabilities. In Journal of real-time image processing (Vol. 3, Nos. 1–2, pp. 21–32). Springer-Verlag. doi:10.1007/s11554-008-0071-3.

  2. Singh, H., Lee, M. H., Lu, G., Kurdahi, F. J., Bagherzadeh, N., & Filho, E. M. C. (2000). Morphosys: An integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Transactions on Computers, 49(5), 465–481.

    Article  Google Scholar 

  3. Mei, B., Vernalde, S., Verkest, D., Man, H. D., & Lauwereins, R. (2003). ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. Field-Programmable Logic and Applications, 2778, 61–70, ISBN 978-3-540-40822-2.

    Article  Google Scholar 

  4. Baumgarte, V., Ehlers, G., May, F., Nuckel, A., Vorbach, M., & Weinhardt, M. (2003). PACT XPP-A self-reconfigurable data processing architecture. The Journal of Supercomputing, 26(2), 167–184.

    Article  MATH  Google Scholar 

  5. Garzia, F., Hussain, W., & Nurmi, J. (2009). CREMA, a coarse-grain re-configurable array with mapping adaptiveness. In Proc. 19th international conference on field programmable logic and applications (FPL 2009). Prague, Czech Republic: IEEE.

    Google Scholar 

  6. Hussain, W., Garzia, F., & Nurmi, J. (2010). Evaluation of Radix-2 and Radix-4 FFT Processing on a Reconfigurable Platform. In Proceedings of the 13th IEEE international symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS’10) (pp. 249–254). IEEE. ISBN 978-1-4244-6610-8.

  7. Garzia, F., Hussain, W., Airoldi, R., & Nurmi, J. (2009). A reconfigurable soc tailored to software defined radio applications. In Proc of 27th Norchip conference. Trondheim (NO).

  8. IEEE Standard for Information Technology–Telecommunications and Information Exchange Between Systems–Local and Metropolitan Area Networks–Specific requirements Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications Amendment 5: Enhancements for Higher Throughput. IEEE, 3 Park Avenue, NY 10016-5997, USA, Oct 2009, E-ISBN: 978-0-7381-6046-7, Print ISBN: 978-0-7381-6047-4.

  9. Bo, F., & Ampadu, P. (2009). An area efficient FFT/IFFT processor for MIMO-OFDM WLAN 802.11n. Journal of Signal Processing Systems, 56, 59–68. ISSN: 1939–8018.

    Article  Google Scholar 

  10. Lin, Y. W., & Lee, C. Y. (2007). Design of an FFT/IFFT processor for MIMO OFDM systems. IEEE Transactions on Circuits and System I, Reg. Papers, 54(4), 807–815.

    Article  MathSciNet  Google Scholar 

  11. Cooley, J. W., & Tukey, J. W. (1965). An algorithm for the machine calculation of complex Fourier series. Mathematics of Computation, 19, 297–301.

    Article  MathSciNet  MATH  Google Scholar 

  12. Hussain, W., Garzia, F., & Nurmi, J. (2010). Exploiting control management to accelerate radix-4 fft on a reconfigurable platform. In Proc. international symposium on system-on-chip 2010 (pp. 154–157). Tampere: IEEE. ISBN: 978-1-4244-8276-4.

    Chapter  Google Scholar 

  13. Kylliainen, J., Ahonen, T., & Nurmi, J. (2007). General-purpose embedded processor cores—the COFFEE RISC example. In J. Nurmi (Ed.), Processor design: System-on-chip computing for ASICs and FPGAs (Ch. 5, pp. 83–100). Kluwer Academic Publishers/Springer Publishers. ISBN-10: 1402055293, ISBN-13: 978-1-4020-5529-4.

  14. Brunelli, C., Garzia, F., Giliberto, C., & Nurmi, J. (2008). A dedicated dma logic addressing a time multiplexed memory to reduce the effects of the system buss bottleneck. In Proc. 18th International conference on field programmable logic and applications, (FPL 2008) (pp. 487–490). Germany: Heidelberg, 8–10 September 2008.

    Chapter  Google Scholar 

  15. Garzia, F., Brunelli, C., & Nurmi, J. (2008). A pipelined infrastructure for the distribution of the configuration bitstream in a coarse-grain reconfigurable array. In Proceedings of the 4th international workshop on Reconfigurable Communication-Centric System-on-Chip (ReCoSoC’08) (pp. 188–191). Univ Montpellier II, ISBN:978-84-691-3603-4.

  16. Garzia, F. (2009). From run-time reconfigurable coarse-grain arrays to application-specific accelerators design, Ph.D. dissertation, Tampere University of Technology (TUT), Department of Computer Systems (DCS), Tampere, Finland, December 2009, 125 pages, TUT Publications 860, ISSN: 1459-2045, ISBN: 978-952-15-2280-2.

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Authors and Affiliations

  1. Department of Computer Systems, Tampere University of Technology, P.O. Box 527, 33101, Tampere, Finland

    Waqar Hussain, Fabio Garzia, Tapani Ahonen & Jari Nurmi

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  1. Waqar Hussain
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  2. Fabio Garzia
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  3. Tapani Ahonen
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  4. Jari Nurmi
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Correspondence to Waqar Hussain.

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Hussain, W., Garzia, F., Ahonen, T. et al. Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems. J Sign Process Syst 69, 161–171 (2012). https://doi.org/10.1007/s11265-011-0642-6

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  • DOI: https://doi.org/10.1007/s11265-011-0642-6

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