Abstract
Instruction Set Simulator (ISS) is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, with the emergence of Chip Multi-Processors, the single-core ISS cannot meet the needs of microprocessor development. In this paper, we introduce our multi-core chip architecture first, after that a general methodology to expand a single-core ISS to a multi-core ISS (MCISS) is proposed. On this basis, a real-time comparison environment is created for multi-core verification, and the problems of multi-core communication and synchronization are addressed gracefully. With the “save and restore” mechanism, the verification procedure and the debugging are speeding up greatly.
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Robinson W H, Alles M L, Bapty T A et al. Soft error considerations for multicore micro-processor design. In Proc. IEEE International Conference on Integrated Circuit Design and Technology, Austin, USA, May 30–June 1, 2007, pp.1–4.
Hu W, Wang J, Gao X et al. Godson-3: A scalable multicore RISC processor with X86 emulation. IEEE Micro, 2009, 29(2): 17–29.
Rosenblum M, Varadajan M. SimOS: A fast operating system simulation environment. Technical Report, CSL-TR-94–631, Stanford University, 1994.
Martin M M, Sorin D J, Beckmann B M et al. Multifacet’s general execution-driven multiprocessor simulator (GEMS) toolset. Computer Architecture News, 2005, 33(4): 92–99.
Glamm B, Lilja D J. Automatic verification of instruction set simulation using synchronized state comparison. In Proc. the 34th Annual Simulation Symposium (SS 2001), Seattle, USA, April 22–26, 2001, pp.72–77.
Taylor S, Quinn M, Brown D et al. Functional verification of a multiple-issue, out-of-order, superscalar alpha processor — The DEC Alpha 21264 microprocessor. In Proc. the 35th Conference on Design Automation, San Francisco, California, USA, June 15–19, 1998, pp.638–643.
Josseo Yim, Park C, Yang W et al. Design verification of complex microprocessors. In Proc. IEEE Asia Pacific Conference on Circuits and Systems, Seoul, Korea, Nov. 18–21, 1996, pp.441–448.
Semeria L, Ghosh A. Methodology for hardware/software co-verification in C/C++. In Proc. ASP-DAC 2000, Yokohama, Japan, Jan. 25–28, 2000, pp.405–408.
Kumar J. UltraSPARC processor emulation verification: Getting HW/SW right the first time. In Proc. DesignCon 2007, Santa Clara, USA, Jan. 29-Feb. 1, 2007, pp.1–17.
Wu Y, Yu L, Lan L et al. A coverage-driven constraint random-based functional verification method of memory controller. In Proc. the 19th IEEE/IFIP International Symposium on Rapid System Prototyping, Monterey, USA, June 2–5, 2008, pp.99–104.
Anderson T L. Open verification methodology: Fulfilling the promise of system verilog. Information Quarterly, 2008, 7(1): 52–54.
Spear C. SystemVerilog for Verification. A Guide to Learning the TestBench Language Features. Springer, 2008, pp.382–419.
MacBeth J S, Heinz D, Gary K. An assembler driven verification methodology (ADVM). In Proc. Design, Automation and Test in Europe Conference and Exposition (DATE 2005), Munich, Germany, March 7–11, 2005, pp.278–283.
Aharon A, Goodman D, Levinger M et al. Test program generation for functional verification of PowerPC processors in IBM. In Proc. IEEE/ACM 32nd Design Automation Conference (DAC), Philadelphia, Pennsylvania, Sept. 10–13, 2006, pp.279–285.
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Hu, XD., Guo, Y., Zhu, Y. et al. Design and Application of Instruction Set Simulator on Multi-Core Verification. J. Comput. Sci. Technol. 25, 267–273 (2010). https://doi.org/10.1007/s11390-010-9323-3
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DOI: https://doi.org/10.1007/s11390-010-9323-3