Abstract
In this work, a novel prescaler based upon new current mode logic (CML) flip-flop architecture applied to global positioning system (GPS) receivers is proposed. Compared to traditional static current mode logic (CML) flip-flop, it introduces a clock-controlling transistor to reduce the time constant at sensing period. As a result, the speed has been maximized and the working range has been enlarged. The phase noise of local oscillator (LO) signals coming from the prescaler can be lowered by 6 dB, and the interference of voltage controlled oscillator (VCO) to radio-frequency (RF) front-end apartments (low noise amplifier, mixer, etc.) will be diminished so that the sensitivity of GPS receivers is enhanced. This prescaler’s maximum input frequency rises up to 6.9 GHz, 30% higher than that of traditional architecture, and its power is only 2.16 mW when the supply voltage is 1.8 V. The prescaler was manufactured in 0.18-μm CMOS process, and it has been successfully applied to GPS receivers.
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Yu, Y., Ye, T. & Ma, C. Optimization and design of a novel prescaler and its application to GPS receivers. Sci. China Inf. Sci. 54, 1938–1944 (2011). https://doi.org/10.1007/s11432-011-4206-y
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DOI: https://doi.org/10.1007/s11432-011-4206-y