Abstract
While scan-based compression is widely utilized in order to alleviate the test time and data volume problems, the overall compression level is dictated not only by the chain to channel ratio but also the ratio of encodable patterns. Aggressively increasing the number of scan chains in an effort to raise the compression levels may reduce the ratio of encodable patterns, degrading the overall compression level. In this paper, we present various methods to improve the ratio of encodable patterns. These methods are based on manipulating the care bit distribution of an unencodable pattern, thereby rendering it compliant with the correlation induced by the decompressor, and thus converting it into an encodable pattern. The proposed transformations, which are simple yet effective, target improvements over fanout and XOR decompressors, while they can be utilized to enhance other types of decompressors, such as multiplexer-based ones; simple nature of these transformations help preserve the simplicity benefits of combinational decompressors. Care bit manipulation is effected in the form of selective chain delay, selective slice rotate/invert, or both. By developing computationally efficient algorithms and cost-effective hardware blocks for these manipulation methods, we show that the encodability, and thus the compression levels, of stimulus decompressors can be significantly improved through the practical and design flow compatible solution that we propose.
Similar content being viewed by others
References
Touba N A. Survey of test vector compression techniques. IEEE Des Test, 2006, 23: 294–303
Jas A, Pouya B, Touba N. Virtual scan chains: a means for reducing scan length in cores. In: VLSI Test Symposium, Montreal, Canada, April, 2000. 73–78
Hamzaoglu I, Patel J H. Reducing test application time for full scan embedded cores. In: Fault Tolerant Computing Symosium, Madison, WI, USA, June, 1999. 260–267
Shah M A, Patel J H. Enhancement of the Illinois scan architecture for use with multiple scan inputs. In: IEEE Computer Society Annual Symposium on VLSI, Lafayette, LA, USA, February, 2004. 167–172
Bayraktaroglu I, Orailoglu A. Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression. In: VLSI Test Symposium, Napa Valley, CA, USA, April, 2003. 113–118
Mitra S, and Kim K S. XPAND: An efficient test stimulus compression technique. IEEE Transactions on Computers, 2006, 55: 163–173
Sitchinava N, Samaranayake S, Kapur R, et al. Changing the scan enable during shift. In: VLSI Test Symposium, Napa Valley, CA, USA, April, 2004. 73–78
Tang H, Reddy S M, Pomeranz I. On reducing test data volume and test application time for multiple scan chain designs, In: International Test Conference, Charlotte, NC, USA, September, 2003. 1070–1088
Koenemann B. LFSR-coded test patterns for scan designs. In: European Test Conference, Munich, Germany, April, 1991. 237–242
Hellebrand S, Rajski J, Tarnick S, et al. In: Generation of vector patterns through reseeding of multiple polynomial LFSRs’. In: International Test Conference, Baltimore, MD, USA, September, 1992. 120–129
Hakmi A W, Wunderlich H J, Zoellin H G, et al. Programmable deterministic built-in self-test. In: International Test Conference, Santa Clara, CA, USA, October, 2007. 1–9
Koenemann B, Barnhart C, Keller B, et al. A SmartBIST variant with guaranteed encoding. In: Asian Test Conference, Kyoto, Japan, November 2001. 325–330
Xiang D, Li K, Sun J, et al. Reconfigured Scan forest for test application cost, test data volume, and test power reduction. IEEE Trans Comput, 2007, 56: 557–562
Miyase K, Kajihara S. Optimal scan tree construction with test vector modification for test compression. In: Asian Test Symposium, Xian, China, November 2003. 136–141
Rajski J, Kassab M, Mukherjee N, et al. Embedded deterministic test for low-cost manufacturing. IEEE Des and Test, 2003, 20: 58–66
Dutta A, Touba N A. Using limited dependence sequential expansion for decompressing test vectors. In: International Test Conference, Santa Clara, CA, USA, October 2006. 2: 657–665
Sinanoglu O. Scan architecture with align-encode. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2008, 27: 2304–2317
Balakrishnan K J, Touba N A. Reconfigurable linear decompressors using symbolic Gaussian elimination. In: Design Automation and Test in Europe Conference, Munich, Germany, March 2005. 1130–1135
Alawadhi N, Sinanoglu O. Improving the effectiveness of XOR-based decompressors through horizontal/vertical move of stimulus fragments. In: Defect and Fault Tolerance Symposium, Chicago, IL, USA, October, 2009. 295–303
Taha M, Alawadhi N, Sinanoglu O, et al. Align-encode delay assignment in the case of XOR-decompressors: Impact of parallel computations. In: WSEAS International Conference on Applied Computer and Applied Computational Science, Hangzhou, China, 2009. 351–359
Alawadhi N, Sinanoglu O, Al-Mulla M. Pattern encodability enhancements for test stimulus decompressors. In: Proceedings of Asian Test Symposium, Shanghai, China, December, 2010. 173–178
Miyase K, Kajiara S. XID: Don’t care identification of test patterns for combinational circuits. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2004, 23: 321–326
Pandey A R, Patel J H. Reconfiguration technique for reducing test time and test data volume in Illinois scan architecture based designs. In: VLSI Test Sympoisum, Monterey, CA, USA, April/May, 2002. 9–16
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Alawadhi, N., Sinanoglu, O. & Al-Mulla, M. Enhancing encoding capacity of combinational test stimulus decompressors. Sci. China Inf. Sci. 54, 1618–1634 (2011). https://doi.org/10.1007/s11432-011-4360-2
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11432-011-4360-2