Abstract
A novel low-power DC offset calibration (DCOC) method independent of intermediate frequency (IF) gain for zero-IF receiver applications has been reported. The conventional analog DCOC method consumes greater power and affects the performance of the receiver. The conventional mixed-signal method requires enhanced memory to store the calibration results at different receiver gains as the DC offset is relative to the radio frequency (RF) and IF gain. A novel algorithm is presented to make the DCOC process independent of IF gain, which significantly reduces the memory area. With the proposed circuit, the receiver calibrates only once so settle-time and power consumption of the IF circuit is lowered. A DCOC circuit with the proposed method is manufactured in 0.18 μm CMOS technology that drains nearly 0 mA equivalent current from a 1.8 V power supply.
摘要
本文基于新型直流失调模型提出了一种应用于零中频接收机的新型直流失调校准方法。 该方法相比于传统的方法, 可以使校准过程独立于零中频接收机的中频增益, 大大简化了校准的复杂度, 有效地降低了校准电路所占用的芯片面积, 节约了芯片成本。 该方法只需要进行一次校准, 平均功耗接近为零, 远低于传统方法的功耗。 基于该方法, 我们实现了一种直流失调校准电路, 实际测试结果与仿真吻合, 很好地证明了该方法的创新性和实用性。
Similar content being viewed by others
References
Razavi B. RF Microelectronics. 2nd Edition. Upper Saddle River: Prentice Hall, 2011
Zheng Y, Yan J, Xu Y. A CMOS VGA with DC offset cancellation for direct-conversion receivers. IEEE Trans Circ Syst I: Reg Papers, 2008, 56: 103–113
Liu S, Wang X, Shen J, et al. A novel compact low-power direct conversion receiver for mobile UHF RFID reader, Sci China Inf Sci, 2012, 55: 2226–2233
Mak P I, Seng-Pan U, Martins R P. On the design of a programmable-gain amplifier with built-in compact DC-offset cancellers for very low-voltage WLAN systems. IEEE Trans Circ Syst I, Reg Papers, 2008, 55: 496–509
Oh S, Park K, Yoo H, et al. A design of DC offset canceller using parallel compensation. In: Proceedings of IEEE International Symposium on Circuits and Systems, New Orleans, 2007. 1685–1688.
Retz G, Shanan H, Mulvaney K, et al. A highly integrated low-power 2.4 GHz transceiver using a direct-conversion diversity receiver in 0.18 μm CMOS for IEEE 802.15.4 WPAN. In: Proceedings of the Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, 2009. 414–415
Shih H, Chen W, Juang K, et al. A 1.2V interference-sturdiness, DC-offset calibrated CMOS receiver utilizing a current-mode filter for UWB. In: Proceedings of IEEE Asian Solid-State Circuits Conference, Fukuoka, 2008. 345–348
Shih H, Kuo C, Chen W, et al. A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR analog baseband chain with digital-assisted DC-offset calibration for ultra-wideband. IEEE J Solid-State Circ, 2010, 45: 338–350
Yang L, Yuan F, Gong Z, et al. A low power mixed signal DC offset calibration circuit for direct conversion receiver applications. J Semicond, 2010, 32: 338–350
Razavi B. Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001
Zhang L W, Jiang H J, Li F L, et al. DC offset calibration method for zero-IF receiver removing the PGA-gaincorrelated offset residue. AEU-Int J Electron Commun, 2013, 67: 578–584
Author information
Authors and Affiliations
Corresponding author
Electronic supplementary material
Rights and permissions
About this article
Cite this article
Dong, J., Jiang, H., Zhang, L. et al. A low-power DC offset calibration method independent of IF gain for zero-IF receiver. Sci. China Inf. Sci. 57, 1–10 (2014). https://doi.org/10.1007/s11432-014-5170-0
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11432-014-5170-0