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References
Qi C H, Xiao L Y, Wang T Q, et al. A highly reliable memory cell design combined with layout-level approach to tolerant single-event upsets. IEEE Trans Dev Mater Rel, 2016, 16: 388–395
Chen J J, Chen S M, Liang B, et al. Simulation study of the layout technique for P-hit single-event transient mitigation via the source isolation. IEEE Trans Dev Mater Relib, 2012, 12: 501–509
Raghuram C H N, Gupta B, Kaushal G. Double node upset tolerant RHBD15T SRAM cell design for space applications. IEEE Trans Dev Mater Relib, 2020, 20: 181–190
Acknowledgements
This work was supported by the Innovation Foundation of Harbin Institute of Technology (Grant Nos. HIT.NSRIF.2019007, 20190028).
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Conclusion
This study proposed a lower power RHBD HP12T SRAM cell. We obtained the following results about HP12T SRAM cell: (1) it can successfully complete normal access and hold operations; (2) it can tolerate heavy-ion striking with LET = 99.8 MeV-cm2/mg even though the charge-sharing effect is considered; (3) it has lower power consumption and comparable access time and SNMs when compared with classical and state-of-the-art SRAM cells.
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Qi, C., Zhang, Y., Ma, G. et al. Design of a high-performance 12T SRAM cell for single event upset tolerance. Sci. China Inf. Sci. 64, 219401 (2021). https://doi.org/10.1007/s11432-020-3123-2
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DOI: https://doi.org/10.1007/s11432-020-3123-2