Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content
Springer Nature Link
Log in

Design and implementation of a highly efficient fractional motion estimation for the HEVC encoder

  • Original Research Paper
  • Published:
Journal of Real-Time Image Processing Aims and scope Submit manuscript

Abstract

This paper presents the VLSI architecture and implementation of the highly efficient fractional motion estimation (FME) for High Efficiency Video Coding (HEVC) systems. In this design, the processing sequence of input pixels is highly optimized so that large parts of the hardware resources in the interpolator circuit are shared and the area complexity is greatly reduced. In order to further enhance the efficiency of hardware utilization and to achieve high throughput, the sum of absolute transformed differences circuit is realized using a pipelined time-multiplexing scheme, and the hardware-sharing structure is utilized to reduce the required computation components. Furthermore, comparing to the literature based on HEVC systems, this design enhances the rate-distortion performance by supporting more prediction modes. The proposed design has been synthesized, placed, and routed through cell-based design flow using TSMC 90-nm technology. The post-layout estimations show that, occupying the area complexity of 525.4 kGE, the presented FME architecture achieves 39 frames per second (fps) with resolution of 3840 × 2160 and 29 fps with resolution of 7680 × 4320. In addition, comparing to the prior art that supports 30 fps and the same number of prediction modes, this design achieves a 2 × improvement of hardware efficiency.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20

Similar content being viewed by others

Notes

  1. We note here that QP = 0 ~ 5 may not be needed in most applications nowadays. However, these experimental results can provide more comprehensive insights and shedding some lights on the design and implementation for HEVC systems targeting on potential very high-quality applications.

  2. It has been reported in [28] that utilizing longer tap filters in HEVC compared to shorter filters in H.264/AVC increases the required memory bandwidth by as high as 51% and increases the required multiply-and-add operations by approximately 20%.

References

  1. Sullivan, G.J., Ohm, J., Han, W.-J., Wiegand, T.: Overview of the high efficiency video coding (HEVC) standard. IEEE Trans. Circuits Syst. Video Technol. 22(12), 1648–1667 (2012)

    Article  Google Scholar 

  2. Ohm, J., Sullivan, G.J., Schwarz, H., Tan, T.K., Wiegand, T.: Comparison of the coding efficiency of video coding standards-including high efficiency video coding (HEVC). IEEE Trans. Circuits Syst. Video Technol. 22(12), 1669–1684 (2012)

    Article  Google Scholar 

  3. Sinangil, M.E., Sze, V., Zhou, M., Chandrakasan, A.P.: Cost and coding efficient motion estimation design considerations for high efficiency video coding (HEVC) standard. IEEE J. Sel. Topics Sign. Process. 7(6), 1017–1028 (2013)

    Article  Google Scholar 

  4. Grellert, M., et al.: An adaptive workload management scheme for HEVC encoding. In: IEEE Int Conference on Image Processing 1850–1854 (2013)

  5. Nightingale, J., Wang, Q., Grecos, C.: HEVStream: a framework for streaming and evaluation of high efficiency video coding (HEVC) content in loss-prone networks. IEEE Trans. Consum. Electron. 58(2), 404–412 (2012)

    Article  Google Scholar 

  6. Ndili, O., Ogunfunmi, T.: Efficient sub-pixel interpolation and low power VLSI architecture for fractional motion estimation in H.264/AVC. In: Proceedings of IEEE International Conference on Signal Processing and Communication Systems, 1–10 (2010)

  7. Ogunfunmi, T., Ndili, T., Arnaudov, P.: On low power fractional motion estimation algorithms for H.264. In: Proceedings of IEEE Workshop on Signal Processing Systems 103–108 (2012)

  8. Song, Y., et al.: H.264/AVC fractional motion estimation engine with computation reusing in HDTV1080p real-time encoding applications. In: Proceedings of IEEE Workshop on Signal Processing Systems 509–514 (2007)

  9. Liu, J., Chen, X., Fan, Y., Zeng, X.: A full-mode FME VLSI architecture based on 8 × 8/4 × 4 adaptive Hadamard transform for QFHD H.264/A VC encoder. In: Proceedings of IEEE International Conference on VLSI and System-on-Chip 434–439 (2011)

  10. Zhou, J., Zhou, D., He, G., Goto, S.: A 1.59 Gpixel/s motion estimation processor with −211-to −211 search range for UHDTV video encoder. IEEE J. Solid State Circuits 49(4), 827–837 (2014)

    Article  Google Scholar 

  11. Pastuszak, G., Jakubowski, M.: Adaptive computationally scalable motion estimation for the hardware H.264/AVC encoder. IEEE Trans. Circuits Syst. Video Technol. 23(5), 802–812 (2013)

    Article  Google Scholar 

  12. Lin, Y.-K., Lin, C.-C., Kuo, T.-Y., Chang, T.-S.: A hardware-efficient H.264/AVC motion-estimation design for high-definition video. IEEE Trans. Circuits Syst. I Regul. Paper 55(6), 1526–1535 (2008)

    Article  MathSciNet  Google Scholar 

  13. Dang, N.-K., Tran, X.-T., Merirot, A.: An efficient hardware architecture for inter-prediction in H.264/AVC encoders. In: Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems 294–297 (2014)

  14. Li, H., Zhang, Y., Chao, H.: An optimally scalable and cost-effective fractional-pixel motion estimation algorithm for HEVC. In: Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing 1399–1403 (2013)

  15. Sotetsumoto, T., Song, T.: Low complexity algorithm for sub-pixel motion estimation of HEVC. In: Proceedings of IEEE International Conference on Signal Processing, Communication and Computing 1–4 (2013)

  16. Jou, S.-Y., Chang, T.-S.: Fast prediction unit selection for HEVC fractional pel motion estimation design. In: Proceedings of IEEE International Conference on Signal Processing Systems 247–250 (2013)

  17. Maich, H., et al.: HEVC fractional motion estimation complexity reduction for real-time applications. In: Proceedings of IEEE Latin American Symposium on Circuits and Systems 1–4 (2014)

  18. Purnachand, N., Alves, L.N., Antonio, N.: Fast motion estimation algorithm for HEVC. In: Proceedings of IEEE International Conference on Consumer Electronics—Berlin 34–37 (2012)

  19. He, G., Zhou, D., Li, Y., Chen, Z., Zhang, T., Goto, S.: High-throughput power-efficient VLSI architecture of fractional motion estimation for ultra-HD HEVC video encoding. IEEE Trans. VLSI Syst. 23(12), 3138–3142 (2015)

    Article  Google Scholar 

  20. Pastuszak, G., Trochimiuk, M.: Algorithm and architecture design of the motion estimation for the H.265/HEVC 4 K-UHD encoder. Springer J. Real Time Image Process. 12(2), 517–529 (2016)

    Article  Google Scholar 

  21. Richardson, I.E.: The H.264 Advanced Video Compression Standard, vol. Ch 6, 2nd edn, pp. 138–177. Wiley, New York (2010)

    Book  Google Scholar 

  22. Pastuszak, G., Trochimiuk, M.: Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder. Springer J. Real Time Image Process. 11554, 1–11 (2014)

    Google Scholar 

  23. Wang, H.-M., Lin, J.-K., Yang, J.-F.: Fast inter mode decision based on hierarchical homogeneous detection and cost analysis for H.264/AVC coders. In: Proceedings of IEEE International Conference on Multimedia and Expo 709–712 (2006)

  24. Lin, Y.-L.S., Kao, C.-Y., Kuo, H.-C., Chen, J.-W.: VLSI Design for Video Coding, vol. Ch 4, 1st edn, pp. 57–72. Springer, New York (2010)

    Book  Google Scholar 

  25. Wang, H., Kwong, S., Kok, C.-W.: An efficient mode decision algorithm for H.264/AVC encoding optimization. IEEE Trans. Multimedia 9, 882–888 (2007)

    Article  Google Scholar 

  26. HEVC software repository—HM-10.1 reference model: https://hevc.hhi.fraunhofer.de/HM-doc/

  27. Ultra-high-definition video group, test sequences: (online). https://media.xiph.org/video/derf/ (2015). Accessed 2 Feb 2015

  28. Sze, V., Budagavi, M., Sullivan, G.J.: High Efficiency Video Coding (HEVC). Springer, New York (2014)

    Book  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan, ROC

    Chun-Yu Lung & Chung-An Shen

Authors
  1. Chun-Yu Lung
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Chung-An Shen
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Chung-An Shen.

Additional information

This work is supported in part by the Ministry of Science and Technology, Taiwan, ROC under Grant MOST 104-2221-E-011-122.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Lung, CY., Shen, CA. Design and implementation of a highly efficient fractional motion estimation for the HEVC encoder. J Real-Time Image Proc 16, 1541–1557 (2019). https://doi.org/10.1007/s11554-016-0663-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11554-016-0663-2

Keywords

Search

Navigation