Abstract
Circuit Testing, in general, is one of the most important projects in the microelectronics industry in which a product's actual performance will be compared with its expected performance. Built-In Self-Test (BIST), is a test by which the Test Pattern Generator (TPG), the Output Response Analyzer (ORA), and the main circuits under test are built on one chip. One of the most important problems in-circuit testing is the increase in power consumption during the test. This occurs for a variety of reasons, including increased switching activity at all nodes and a lack of correlation between input patterns in the experimental mode compared to the normal state. In this paper, counters and combined circuits are used to reduce power consumption. Contrary to other methods, in this method, only the required test patterns are generated. Abstaining of producing ineffective patterns in the circuit under test results in a reduction in the power consumption. Besides, effective experimental patterns are produced with fewer flip-flops. Experimental results obtained by analyzing Synopsys Design Compiler software on several circuits of ISCAS'89 and EPFL benchmarks show that in ISCAS 89 benchmark, the switching power in the proposed design is 42.43 less than LSFR and 10.42% less than ROM, and in EPFL it is 38% and 12.21% less for LSFR and ROM respectively.
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Amarú L, Gaillardon PE, De Micheli G (2015) The EPFL combinational benchmark suite. In: Proceedings of the 24th International Workshop on Logic & Synthesis (IWLS) (No. CONF)
Balaji GN, Pandian SC (2019) Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates. Clust Comput. https://doi.org/10.1007/s10586-018-2552-x
Brglez F, Bryan D, Kozminski K (1989) Notes on the ISCAS'89 benchmark circuits. North-Carolina State University
Chen T, Zheng L, Wang W, Ren F, Zhang X, Chang H (2014) A low power BIST scheme based on block encoding. In: Fifth International Conference on Computing, Communications and Networking Technologies (ICCCNT), 1–7. https://doi.org/10.1109/ICCCNT.2014.6963020
Chung EY, Benini L, Bogliolo A, Lu YH, De Micheli G (2002) Dynamic power management for nonstationary service requests. IEEE Trans Comput 51(11):1345–1361. https://doi.org/10.1109/TC.2002.1047758
Deepsita S, Sk N (2019) Energy Efficient Binary Adders for Error Resilient Applications. In: 2019 IEEE Conference on Modeling of Systems Circuits and Devices, 23–28. https://doi.org/10.1109/MOS-AK.2019.8902400
Gopalan K, Pothiraj S (2020) A saboteur and mutant based built-in self-test and counting threshold-based built-in self repairing mechanism for memories. J Ambient Intell Humaniz Comput. https://doi.org/10.1007/s12652-020-02284-5
Hussain S, Rao VM (2017) An SIC-BS linear feedback shift register for low power BIST. In: 2017 Devices for Integrated Circuit, 606–610. https://doi.org/10.1109/DEVIC.2017.8074022
Jamal K, Chari KM, Srihari P (2019) Test pattern generation using thermometer code counter in TPC technique for BIST implementation. Microprocess Microsyst. https://doi.org/10.1016/j.micpro.2019.102890
Lala P (2008) An introduction to logic circuit testing. Synthesis Lectures Digital Circuits Syst. https://doi.org/10.2200/S00149ED1V01Y200808DCS017
Li W, Ning H, Yu Z, Shi Y, Wang X (2019) Reducing the power consumption of two-dimensional logic transistors. J Semicond. https://doi.org/10.1088/1674-4926/40/9/091002
Magen N, Kolodny A, Weiser U, Shamir N (2004) Interconnect-power dissipation in a microprocessor. In: Proceedings of the 2004 international workshop on System level interconnect prediction, 7–13. https://doi.org/10.1145/966747.966750
Mishra BJ, Saraswat R (2016) Low power BIST based multiplier design and simulation using FPGA. In: 2016 IEEE Students' Conference on Electrical, Electronics and Computer Science (SCEECS), 1–6. https://doi.org/10.1109/SCEECS.2016.7509284
Mohan M, Pillai SS (2019) Review on LFSR for Low Power BIST. In: 2019 3rd International Conference on Computing Methodologies and Communication (ICCMC), 873–876. https://doi.org/10.1007/s12652-020-02284-5
Mohan N, Kumar MA, Dhanush D, Prasath J (2020) Low transition dual LFSR for low power testing. Invent Commun Comput Technol. https://doi.org/10.1007/978-981-15-7345-3_33
Moryani B, Mishra DK (2017) Low power test pattern generator with modified clock for BIST. In: 2017 International Conference on Recent Innovations in Signal processing and Embedded Systems, https://doi.org/10.1109/RISE.2017.8378189
Mosalgi M, Hegde G (2017) Power Optimized TPG for BIST Architecture. In: 2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), 1–4. https://doi.org/10.1109/ICCIC.2017.8524577
Murugan SV, Sathiyabhama B (2020) Bit-swapping linear feedback shift register (LFSR) for power reduction using pre-charged XOR with multiplexer technique in built in self-test. J Ambient Intell Humaniz Comput. https://doi.org/10.1007/s12652-020-02222-5
Nose K, Sakurai T (2000) Analysis and future trend of short-circuit power. IEEE Trans Comput Aided Des Integr Circuits Syst 19(9):1023–1030. https://doi.org/10.1109/43.863642
Praveen J, Shanmukha Swamy MN (2018) BIST-based low power test vector generator and minimizing bulkiness of VLSI architecture. J Circuits Syst Comput. https://doi.org/10.1142/S0218126618500780
Puczko M (2015) Low power test pattern generator for BIST. In: 2015 Selected Problems of Electrical Engineering and Electronics (WZEE), 1–6. https://doi.org/10.1109/WZEE.2015.7394030
Sankari GS, Maheswari M (2018) Energy efficientweighted test pattern generator based bist architecture. In: 2018 2nd International Conference on I-SMAC, 448–453. https://doi.org/10.1109/I-SMAC.2018.8653768
Sanyal A, Rastogi A, Chen W, Kundu S (2010) An efficient technique for leakage current estimation in nanoscaled CMOS circuits incorporating self-loading effects. IEEE Trans Comput 59(7):922–932. https://doi.org/10.1109/TC.2010.75
Saraswathi R, Manikandan R (2017) Design of LFSR (linear feedback shift register) for low power test pattern generator. In: 2017 International Conference on Networks & Advances in Computational Technologies, 317–322. https://doi.org/10.1109/NETACT.2017.8076788
Swami Y, Rai S (2017) Modeling and analysis of sub-surface leakage current in nano-MOSFET under cutoff regime. Superlattices Microstruct. https://doi.org/10.1016/j.spmi.2016.12.044
Syamala Y, Tilak AV, Srilakshmi K, Anil CT (2018) Low Power Testable Reversible Combinational Circuits. In: 2018 Second International Conference on Intelligent Computing and Control Systems, 1485–1489. https://doi.org/10.1109/ICCONS.2018.8663240
Xiang D, Wen X, Wang LT (2016) Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 942–953. https://doi.org/10.1109/TVLSI.2016.2606248
Ying JC, Tseng WD, Tsai WJ (2018) Asymmetry dual-LFSR reseeding for low power BIST. Integration 60:272–276. https://doi.org/10.1016/j.vlsi.2017.10.012
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Askarzadeh, M., Haghparast, M. & Jabbehdari, S. Power consumption reduction in built-in self-test circuits. J Ambient Intell Human Comput 14, 1109–1122 (2023). https://doi.org/10.1007/s12652-021-03363-x
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DOI: https://doi.org/10.1007/s12652-021-03363-x