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A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO

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Abstract

We propose a compact coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function ECHO on Virtex-5 and Virtex-6 FPGAs. Our architecture is built around an 8-bit datapath. The Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and ECHO at all levels of security. Thanks to a careful organization of AES and ECHO internal states in the register file, we manage to generate all read and write addresses by means of a modulo-16 counter and a modulo-256 counter. A fully autonomous implementation of ECHO and AES on a Virtex-5 FPGA requires 193 slices and a single 36k memory block, and achieves competitive throughputs. Assuming that the security guarantees of ECHO are at least as good as the ones of the SHA-3 finalists BLAKE and Keccak, our results show that ECHO is a better candidate for low-area cryptographic coprocessors. Furthermore, the design strategy described in this work can be applied to combine the AES and the SHA-3 finalist Grøstl.

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Authors and Affiliations

  1. Graduate School of Systems and Information Engineering, University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki, 305-8573, Japan

    Jean-Luc Beuchat, Eiji Okamoto & Teppei Yamazaki

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  1. Jean-Luc Beuchat
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  2. Eiji Okamoto
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  3. Teppei Yamazaki
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Correspondence to Jean-Luc Beuchat.

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Beuchat, JL., Okamoto, E. & Yamazaki, T. A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO. J Cryptogr Eng 1, 101–121 (2011). https://doi.org/10.1007/s13389-011-0009-8

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  • DOI: https://doi.org/10.1007/s13389-011-0009-8

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