Abstract
Low-dropout (LDO) regulators are becoming a part of modern processor architectures for fine-grain power management and higher energy efficiency. This paper shows that these integrated LDOs can also be leveraged to enhance side-channel analysis resistance of encryption engines to power side-channel analysis (PSCA) attacks. The current transformation induced by integrated LDOs coupled with limited bandwidth of the feedback loop help suppress the side-channel leakage. The impact of both analog LDO (ALDO) and all-digital LDO (ADLDO) on the load currents is studied with correlation analysis between the load and the LDO input current. The effectiveness of integrated LDOs as countermeasure to PSCA is further explored with Correlation Power Analysis (CPA) and Test Vector Leakage Assessment (TVLA) performed on both simulated as well as measured load currents for a 128-bit Advanced Encryption Standard (AES) implemented in GF-130-nm process technology. We show that integrated LDOs can enhance PSCA resistance; however, the trade-off between integrated LDO performance and side-channel security is essential. We design integrated LDOs optimized for low-power/compact encryption engines and show that LDO-based protection can increase power attack resistance by >800× with minimal power, area, and performance overheads.
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References
Paul C et al (1999) Differential power analysis. Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology. pp 388–397
Bo Y et al (2012) An AES chip with DPA resistance using hardware-based random order execution. J Semicond 33(6):1–8
Ambrose JA et al (2008) MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm. International Conference on Computer-Aided Design (ICCAD), IEEE/ACM
Ghellar F et al (2008) A novel AES cryptographic core highly resistant to differential power analysis attacks. Proceedings of the 21st annual symposium on Integrated circuits and system design. pp 140–145
Kaps J et al ( 2010) DPA resistant AES on FPGA using partial DDL. Field-Programmable Custom Computing Machines (FCCM). pp 273-80, IEEE
Amouri E et al (2014) Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL. pp 1–4, IEEE
Popp T, Kirschbaum M, Zefferer T, Mangard S (2007) Evaluation of the masked logic style MDPL on a prototype chip. In: Paillier P, Verbauwhede I (eds) Cryptographic Hardware and Embedded Systems - CHES 2007. CHES 2007. Lecture Notes in Computer Science, vol 4727. Springer, Berlin, Heidelberg
Tokunaga C et al (2009) Secure AES engine with a local switched-capacitor current equalizer. International Symposium on Solid State Circuits (ISSCC), IEEE
Wang X et al (2013) Role of power grid in side channel attack and power-grid-aware secure design. Design Automation Conference (DAC), ACM
Menicocci R et al (2014) Experiments on two clock countermeasures against power analysis attacks. Mixed Design of Integrated Circuits (MIXDES), IEEE
Suzuki D, Saeki M (2006) Security evaluation of DPA countermeasures using dual-rail pre-charge logic style. In: Cryptographic hardware and embedded systems (CHES), LNCS, vol 4249. Springer, Berlin, pp 255–269
Telandro V et al (2006) On-chip voltage regulator protecting against power analysis attacks. Mid-West Circuits and Systems (MWCAS), IEEE
Ozun O et al (2014) Converter-gating: a power efficient and secure on-chip power delivery system. IEEE J Emerging Sel Top Circuits Syst (JETCAS) 4(2):69–179
Yu W et al (2015) Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks. Design automation conference (DAC)
Kar M et al (2014) Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study. Custom Integrated Circuits Conference (CICC)
Kar M et al (2016) Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. Proceedings of the 2016 International Symposium on Low Power Electronics and Design (ISLPED). pp 130–135
Kar M et al (2017) Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator. IEEE International Solid-State Circuits Conference (ISSCC). pp 142–143
Singh A et al (2017) Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering. European Solid State Circuits Conference
Singh A et al (2015) Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators. International Symposium on Low Power Electronics and Design (ISLPED). pp 134–139
Singh A et al (2016) Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators. International Symposium on Hardware Security and Trust (HOST). pp 145–148
Das D et al (2017) High efficiency power side-channel attack immunity using noise injection in attenuated signature domain. International Symposium on Hardware Security and Trust (HOST)
Gangopadhyay S et al (2014) A 32-nm embedded, fully-digital, phase-locked low dropout regulator for fine grained power management in digital circuits. IEEE J Solid State Circuits 49(11):2684–2693
Toprak-Deniz Z et al (2014) Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. International symposium on solid state circuits (ISSSC)
Torres J et al (2014) Low drop-out voltage regulators: capacitor-less architecture comparison. IEEE Circuits Syst Mag 14(2):6–26
Bulzacchelli JF et al (2012) Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500 ps, and 85-mV dropout voltage. IEEE J Solid State Circuits 47(4):863–874
Nasir SB et al (2015) A 0.13μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range. International symposium on solid state circuits (ISSSC)
Brier E, Clavier C, Olivier F (2004) Correlation power analysis with a leakage model. In: Joye M, Quisquater JJ (eds) Cryptographic hardware and embedded systems - CHES 2004. CHES 2004. Lecture Notes in Computer Science, vol 3156. Springer, Berlin, Heidelberg
Guilley S et al (2011) Quantifying the quality of side channel acquisitions. Constructive Side Channel analysis and secure design (COSADE)
Kress D (2011) Understanding ac behaviors of high speeds ADCs. Technical Article, Analog Devices
Chen W et al (2014) A switchable digital–analog low-dropout regulator for analog dynamic voltage scaling technique. IEEE J Solid State Circuits 49(3):740–750
Otsuga K et al (2012) An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor. SOC Conference (SOCC)
Onouchi M et al (2011) A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process. Asian solid state circuits conference (A-SSSCC)
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This material is based on a work supported in part by Intel Corp. and National Science Foundation.
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Singh, A., Kar, M., Mathew, S. et al. Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators. J Hardw Syst Secur 1, 340–355 (2017). https://doi.org/10.1007/s41635-017-0023-0
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DOI: https://doi.org/10.1007/s41635-017-0023-0