Abstract
Embedded workloads are increasing day by day and becoming more complex. The number of workloads running in the embedded processors has been growing exponentially for the past few decades owing to the increased penetration of Internet of Things (IoT) among the users. Realizing the growing demand and complexity of the embedded workloads, embedded CPU designs are migrated from the single core to multiple cores to cater the needs of user’s application. But still, energy consumption, intelligent handling of the workloads still remains to be the real challenge among the researchers. To cater these challenges in realizing the full potential of the underlying platform, this paper proposes the deep learning-based workload characterization technique in which the microarchitecture independent workloads are considered as the major inputs. These inputs are then used for training the novel deep learning network called Bi-Attention–LSTM (Long Short Term Memory) which categorize the workloads in accordance to the present characteristics of embedded processors. The microarchitecture-independent workloads are collected from the three different benchmarks namely MiBENCH, IoMT (Internet of Medical Things) and EEMBC workloads thereby conducting the comprehensive experimentation to validate the proposed framework. The performance of characterization is then contrasted with that of other cutting-edge deep learning frameworks to demonstrate the superior performance of the proposed framework. Findings demonstrate that the suggested framework has outperformed the other frameworks with the finds its strong place in the workload characterization for multi core embedded processors.
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This article is part of the topical collection “Advances in Computational Approaches for Image Processing, Wireless Networks, Cloud Applications and Network Security” guest edited by P. Raviraj, Maode Ma and Roopashree H R.
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Sivaramakrishnan, R., Senthilkumar, G. A Deep Learning Framework for Microarchitecture Independent Workload Characterization Technique for Multi-core Asymmetric Embedded Systems. SN COMPUT. SCI. 4, 511 (2023). https://doi.org/10.1007/s42979-023-01909-8
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DOI: https://doi.org/10.1007/s42979-023-01909-8