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Hardware Security of Image Processing Cores Against IP Piracy Using PSO-Based HLS-Driven Multi-Stage Encryption Fused with Fingerprint Signature

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Abstract

The increasing usage of image processing applications in modern technological environments is driven by their ability to enhance visual quality in diverse applications, from social media to medical imaging. The design of these cores as dedicated application-specific hardware intellectual property (IP) must ensure optimized performance and security. It is crucial to optimize these designs while enhancing their security to create a robust, secure design flow that can provide security against hardware security threats like IP piracy and fraudulent ownership claim. The proposed methodology introduces a low-cost security framework for application-specific hardware systems using an HLS-aided fusion watermarking framework and particle swarm optimization-driven design space exploration (PSO-DSE) process. The proposed approach demonstrates the generation of a multi-stage encryption-based signature along with the IP seller’s fingerprint biometric-based signature, which is further fused to generate the final watermark signature. It allows the embedding of a greater number of secret watermark constraints offering lower probability of coincidence and higher tamper tolerance without incurring design overhead, compared to prior works.

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Availability of Data and Material

The datasets used and/or analyzed during the current study is available from the corresponding author on reasonable request.

References

  1. Schneiderman R. DSPs Evolving in consumer electronics applications. IEEE Signal Process Mag. 2010;27(3):6–10.

    Article  Google Scholar 

  2. Anshul A, Sengupta A. A survey of high level synthesis based hardware security approaches for reusable IP cores. IEEE Circuits Syst Magaz. 2023;23(4):44–62.

    Article  Google Scholar 

  3. Anshul A, Sengupta A. Low-cost hardware security of laplace edge detection and embossment filter using HLS based encryption and PSO. 2023 IEEE International Symposium on Smart Electronic Systems (iSES), Ahmedabad, India, 2023;135–140.

  4. Yu T, Zhu. A new watermarking method for soft IP protection. 2011 International Conference on Consumer Electronics, Communications and Networks (CECNet), Xianning, China 2011;3839–3842.

  5. Rostami M, Koushanfar F, Karri R. A primer on hardware security: models, methods, and metrics. Proc IEEE. 2014;102(8):1283–95.

    Article  Google Scholar 

  6. Islam SA, Sah LK, Katkoori S. High-level synthesis of key-obfuscated RTL IP with design lockout and camouflaging. ACM Trans. Des. Autom. Electron. Syst. 2021;26(1), Article 6.

  7. Koushanfar F et al. Can EDA combat the rise of electronic counterfeiting? Design Automation Conference 2012, San Francisco, CA, USA, 2012;133–138.

  8. Kao Y, Chen M, Huang Y. A hybrid algorithm based on ACO and PSO for capacitated vehicle routing problems. Math Prob Eng. 2012. https://doi.org/10.1155/2012/726564.

    Article  MathSciNet  Google Scholar 

  9. Sengupta A, Bhadauria S. Automated exploration of datapath in high level synthesis using temperature dependent bacterial foraging optimization algorithm. IEEE 27th Canadian Conference on Electrical and Computer Engineering (CCECE), 2014; pp. 1–5.

  10. Krishnan V, Katkoori S. A genetic algorithm for the design space exploration of datapaths during high-level synthesis. IEEE Trans Evol Comput. 2006;10(3):213–29.

    Article  Google Scholar 

  11. Mishra VK, Sengupta A. MO-PSE: adaptive multi objective particle swarm optimization based design space exploration in architectural synthesis for application specific processor design. Elsevier J Adv Eng Software. 2014;67:111–24.

    Article  Google Scholar 

  12. Anshul A. Sengupta, exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis. Elsevier J Microprocess Microsyst. 2023;102: 104916.

    Article  Google Scholar 

  13. Zhao F, Tang X. Preprocessing and postprocessing for skeleton-based fingerprint minutiae extraction. Pattern Recogn. 2007;40(4):1270–81.

    Article  Google Scholar 

  14. Koushanfar F, Hong I, Potkonjak M. Behavioral synthesis techniques for intellectual property protection. ACM Trans Des Autom Electron Syst. 2005;10:523–45.

    Article  Google Scholar 

  15. Sengupta A, Bhadauria S. Exploring low cost optimal watermark for reusable IP cores during high level synthesis. IEEE Access. 2016;4:2198–215.

    Article  Google Scholar 

  16. Gal L, Bossuet L. Automatic low-cost IP watermarking technique based on output mark insertions. Des Autom Embedded Syst. 2012;16:71–92.

    Article  Google Scholar 

  17. Sengupta A, Rathor M. IP core steganography for protecting DSP kernels used in CE systems. IEEE Trans Consum Electron. 2019;65(4):506–15.

    Article  Google Scholar 

  18. Sengupta A, Chaurasia R. Securing IP cores for DSP applications using structural obfuscation and chromosomal DNA impression. IEEE Access. 2022;10:50903–13.

    Article  Google Scholar 

  19. Castillo E, Parrilla L, Garcia A, Meyer-Baese U, Botella G, Lloris A. Automated signature insertion in combinational logic patterns for HDL IP core protection. 2008 4th Southern Conference on Programmable Logic, Bariloche, Argentina, 2008;183–186.

  20. Sengupta A, Chaurasia R, Reddy T. Contact-less palmprint biometric for securing DSP coprocessors used in CE systems. IEEE Trans Consum Electron. 2021;67(3):202–13.

    Article  Google Scholar 

  21. Chen J, Schafer BC. Watermarking of behavioral IPs: a practical approach. 2021 IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2021.

  22. Sadangi S, Baraha S, Satpathy DK, Biswal PK. FPGA implementation of spatial filtering techniques for 2D images. In Proc. RTEICT 2017;1213–1217.

  23. Tsiktsiris D, Ziouzios D, Dasygenis M. A portable image processing accelerator using FPGA. In Proc. MOCAST, 2018;1–4.

  24. Davalle D, Carnevale B, Saponara S, Fanucci L, Terreni P. Hardware accelerator for fast image/video thinning. In Proc. IST, 2014;64–67.

  25. Shu W, Pang H, Liu S. High energy efficiency FPGA based accelerator for convolutional neural networks using weight combination. In Proc. ICSIP, Wuxi, China, 2019;578–582.

  26. Choi SB, Lee SS, Jang SJ. CNN inference simulator for accurate and efficient accelerator design. In Proc. ISOCC, Jeju, South Korea, 2019;283–284.

  27. Potkonjak M. Methods and systems for the identification of circuits and circuit designs. USPTO, US7017043B1 2006.

  28. Lebreton L, Coussy G, Martin P. Hierarchical and multiple-clock domain high-level synthesis for low-power design on FPGA. In Proceedings of international conference on field programmable logic and applications, 2010;464– 468.

  29. Liu H-Y, Carloni LP. On learning-based methods for design-space exploration with high-level synthesis. In Proceedings of design automation conference, 2013;pp. 1–7.

  30. Zhang Z, Fan Y, Jiang W, Han G, Yang C, Cong J. AutoPilot: a platform-based ESL synthesis system. In Proceedings in high-level synthesis, Springer, 2008;99–112.

  31. Williams C, Brown AD, Zwolinski M. Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis. Proc IEEE Comput Digital Techn. 2008;147(6):383–90.

    Article  Google Scholar 

  32. Hu W, Chang C-H, Sengupta A, Bhunia S, Kastner R, Li H. An overview of hardware security and trust: threats, countermeasures, and design tools. IEEE Trans Comput Aided Des Integr Circuits Syst. 2021;40(6):1010–38.

    Article  Google Scholar 

  33. OCL, 15 nm open cell library. [Online], Available: https://si2.org/open-cell-library/, last Accessed on may. 2024.

  34. University of California Santa Barbara Express Group, accessed on May. 2024. [Online]. Available: http://express.ece.ucsb.edu/benchmark.

  35. Wihartiko F, Wijayanti H, Virgantari F. Performance comparison of genetic algorithms and particle swarm optimization for model integer programming bus timetabling problem. IOP Conference Series Mater Sci Eng. 2018;332: 012020.

    Article  Google Scholar 

  36. Zukhri Z, Islam U, Zukhri Z. A hybrid optimization algorithm based on genetic algorithm and ant colony optimization. Int J Artific Intellig Applic. 2013;4:63–75.

    Google Scholar 

  37. Sengupta S. Bhadauria, Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis. Expert Syst Appl. 2015;42(10):4719–32.

    Article  Google Scholar 

  38. NIST, Accessed on Aug. 2024. [Online]. Available: https://csrc.nist.gov/csrc/media/Presentations/2022/security-of-hardware/3-Rekhi%202pm%20Security%20of%20Hardware.pdf

  39. FORTINET, Accessed on Aug. 2024. [Online]. Available: https://www.fortinet.com/resources/cyberglossary/hardware-security-module.

  40. Sengupta A, Bhadauria S, Mohanty SP. TL-HLS: methodology for low cost hardware trojan security aware scheduling with optimal loop unrolling factor during high level synthesis. IEEE Trans Comput Aided Design Integrat Circuits Syst. 2017;36(4):655–68.

    Article  Google Scholar 

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Acknowledgements

This work is technically and financially supported by CSIR grant no. 22/0856/23/EMR-II.

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Contributions

Anirban Sengupta: Problem formulation, Ideation, Technical supervision. Aditya Anshul: Development and implementation of the idea, Writing the research paper.

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Correspondence to Aditya Anshul.

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Sengupta, A., Anshul, A. Hardware Security of Image Processing Cores Against IP Piracy Using PSO-Based HLS-Driven Multi-Stage Encryption Fused with Fingerprint Signature. SN COMPUT. SCI. 5, 941 (2024). https://doi.org/10.1007/s42979-024-03255-9

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