Abstract
Unique designs for CMOS analog arithmetic circuits are presented which perform addition (V1 + V2), subtraction (V2 − V1), add/invert −(V1 + V2), and multiply (V1 × V2). The circuit operation is based on the inherent square law of MOS transistor drain current when operating in the saturation region. Key features include: good linearity and accuracy, single ended voltage inputs and output, wide input and output range and no input bias voltages. The circuits can be directly coupled (no buffer) and serve as basic building blocks for analog signal processing implementations such as analog filters and adaptive equalizers. All circuits were implemented in 1.2 μm CMOS technology.
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Xu, J., Siferd, R. & Ewing, R.L. High Performance CMOS Analog Arithmetic Circuits. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 22, 103–111 (1999). https://doi.org/10.1023/A:1008143206419
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DOI: https://doi.org/10.1023/A:1008143206419