Abstract
The contributions of this paper are twofold. First, an automatic tool-based approach is described to bound worst-case data cache performance. The approach works on fully optimized code, performs the analysis over the entire control flow of a program, detects and exploits both spatial and temporal locality within data references, and produces results typically within a few seconds. Results obtained by running the system on representative programs are presented and indicate that timing analysis of data cache behavior usually results in significantly tighter worst-case performance predictions. Second, a method to deal with realistic cache filling approaches, namely wrap-around-filling for cache misses, is presented as an extension to pipeline analysis. Results indicate that worst-case timing predictions become significantly tighter when wrap-around-fill analysis is performed. Overall, the contribution of this paper is a comprehensive report on methods and results of worst-case timing analysis for data caches and wrap-around caches. The approach taken is unique and provides a considerable step toward realistic worst-case execution time prediction of contemporary architectures and its use in schedulability analysis for hard real-time systems.
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References
Aho, A. V., Sethi, R., and Ullman, J. D. 1986. Compilers — Principles, Techniques, and Tools. Addison-Wesley.
Arnold, R., Mueller, F., Whalley, D. B., and Harmon, M. 1994. Bounding worst-case instruction cache performance. IEEE Real-Time Systems Symposium, pp. 172–181.
Audsley, N., Burns, A., Davis, R., Tindell, K., and Wellings, A. J. 1995. Fixed priority pre-emptive scheduling: An historical perspective. J.Real-Time Systems 8: 173–198.
Benitez, M. E., and Davidson, J. W. 1988. A portable global optimizer and linker. ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 329–338.
Chapman, B., Mehrotra, P., and Zima, H. 1992. Programming in vienna fortran. Contractor Report 189623, NASA Langley Research Center.
Chapman, B., Mehrotra, P., and Zima, H. 1993. High performance fortran without templates. Contractor Report 191451, NASA Langley Research Center.
Chapman, B., Mehrotra, P., and Zima, H. 1994. Extending hpf for advanced data parallel applications. Contractor Report 194913, NASA Langley Research Center.
Davidson, J. W., and Whalley, D. B. 1991. A design environment for addressing architecture and compiler interactions. Microprocessors and Microsystems 15(9): 459–472.
Harmon, M., Baker, T. P., and Whalley, D. B. 1992. A retargetable technique for predicting execution time. IEEE Real-Time Systems Symposium, pp. 68–77.
Healy, C. A., Arnold, R. D., Mueller, R., Whalley, D., and Harmon, M. G. 1999. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers 48(1): 53–70.
Healy, C. A., Whalley, D. B., and Harmon, M. G. 1995. Integrating the timing analysis of pipelining and instruction caching. IEEE Real-Time Systems Symposium, pp. 288–297.
Hennessy, J., and Patterson, D. 1996. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 2nd edition.
Hur, Y., Bae, Y. H., Lim, S.-S., Rhee, B.-D., Min, S. L., Park, C. Y., Lee, M., Shin, H., and Kim, C. S. 1995. Worst case timing analysis of RISC processors: R3000/R3010 case study. IEEE Real-Time Systems Symposium, pp. 308–319.
Kim, S., Min, S., and Ha, R. 1996. Efficient worst case timing analysis of data caching. IEEE Real-Time Technology and Applications Symposium.
Li, Y.-T. S., Malik, S., and Wolfe, A. 1995. Efficient microarchitecture modeling and path analysis for real-time software. IEEE Real-Time Systems Symposium, pp. 298–397.
Li, Y.-T. S., Malik, S., and Wolfe, A. 1996. Cache modeling for real-time software: Beyond direct mapped instruction caches. IEEE Real-Time Systems Symposium, pp. 254–263.
Lim, S.-S., Bae, Y. H., Jang, G. T., Rhee, B.-D., Min, S. L., Park, C. Y., Shin, H., and Kim, C. S. 1994. An accurate worst case timing analysis for RISC processors. IEEE Real-Time Systems Symposium, pp. 97–108.
Liu, C. L., and Layland, J.W. 1973. Scheduling algorithms for multiprogramming in a hard-real-time environment. Journal of the Association for Computing Machinery 20(1): 46–61.
Mueller, F. 1994. Static cache simulation and its applications. PhD thesis, Dept. of CS, Florida State University.
Park, C. Y. 1993. Predicting program execution times by analyzing static and dynamic program paths. Real-Time Systems 5(1): 31–61.
Polychronopoulos, C. D. 1988. Parallel Programming and Compilers. Kluwer.
Puschner, P. 1993. Zeitanalyse von Echtzeitprogrammen. PhD thesis, Dept. of CS, Technical University Vienna.
Puschner, P., and Koza, C. 1989. Calculating the maximum execution time of real-time programs. Real-Time Systems 1(2): 159–176.
Rawat, J. 1995. Static analysis of cache analysis for real-time programming. Master's thesis, Iowa State University.
Texas Instruments. 1993. TMS390S10 Integrated SPARC Processor.
White, R. 1997. Bounding worst-case data cache performance. PhD thesis, Dept. of Computer Science, Florida State University.
White, R., Mueller, F., Healy, C., Whalley, D., and Harmon, M. 1997. Timing analysis for data caches and set-associative caches. IEEE Real-Time Technology and Applications Symposium, pp. 192–202.
Wolfe, M. 1989. Optimizing Supercompilers for Supercomputers. MIT Press.
Wolfe, M. 1996. High Performance Compilers for Parallel Computing. Addison-Wesley.
Zhang, N., Burns, A., and Nicholson, M. 1993. Pipelined processors and worst case execution times. Real-Time Systems 5(4): 319–343.
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White, R.T., Mueller, F., Healy, C. et al. Timing Analysis for Data and Wrap-Around Fill Caches. Real-Time Systems 17, 209–233 (1999). https://doi.org/10.1023/A:1008190423977
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DOI: https://doi.org/10.1023/A:1008190423977