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On-Chip Weighted Random Patterns

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Abstract

Even though there has been a considerable effort in proposing weighted random pattern testing schemes over the years, insufficient attention has been devoted to their implementation. This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP SRLs designed specifically to facilitate a weighted random pattern (WRP) test. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to “go after” the remaining untested faults. The cost and performance of this design system are explored on ten pilot chips. Results of this experiment are provided in the paper.

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Authors and Affiliations

  1. ECE Department, New Jersey Institute of Technology, University Heights, Newark, New Jersey, 07102-1982

    Jacob Savir

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  1. Jacob Savir
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Savir, J. On-Chip Weighted Random Patterns. Journal of Electronic Testing 13, 41–50 (1998). https://doi.org/10.1023/A:1008385116436

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  • DOI: https://doi.org/10.1023/A:1008385116436

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