Abstract
In this paper we show that some expressions frequently used in multimedia applications can be formulated as a general add-multiply-add operation. We further show a hardwired implementation of the Add-Multiply-Add instruction which is no more complex than the multiplier implementation. Furthermore we show that two frequently motion estimation operations, the Sum and Mean of Absolute Differences, can be implemented in hardware requiring also approximately the same cycle time as the multiplication. We also show that our approach can be extended easily to provide the computation of the Sum and Mean of Absolute Difference of a 16×16 pixel block in no more than four machine cycles. Additionally we propose a codec hardwired mechanism for the Paeth predictor used in the Portable Network Standard (PNG) that requires at most two general purpose ALU cycles. We extend the paeth unit to include the median, maximum and minimum operations on three inputs with no additional cycle time and we also extend the Add-Multiply-Add unit to include the mean of three numbers. Finally we propose a multimedia hardware accelerator to accommodate all the proposed operations. The proposed unit is an extension of the multiply pipeline with ALU extensions with no extra stages added. The unit operates on 32 instructions in total.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
K. Aono, M. Toyokura, T. Araki, A. Ohtani, H. Kodama, and K. Okamoto, "A Video Digital Signal Processor with a Vector-Pipeline Architecture," IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, pp. 1886–1894, December 1992.
P.A. Ruetz, P. Tong, D. Bailey, D.A. Luthi, and P.H. Ang, "A High-Performance Full-Motion Video Compression Chip Set,"IEEE Transactions on Circuits and Systems for Video Technol-ogy, Vol. 2, No. 2, pp. 111–122, June 1992.
K. Herrmann, M. Seifert, K. Gaedke, H. Jeschke, and P. Pirsch, Architecture and VLSI Implementation of a RISC Core for a Monolithic Video Signal Processor, VLSI Signal Processing. New York: IEEE, 1994, pp. 368–377.
S. Rathnam and G. Slavenburg, "An Architectural Overview of the Programmable Multimedia Processor, TM-1," in Proceedings of COMPCON '96, IEEE, 1996, pp. 319–326, Los Alamitos, 25–28 February 1996.
K. Guttag, R.J. Gove, and J.R. van Aken, "A Single-Chip Multi-Processor for Multimedia: The MVP," IEEE Computer Graphics and Applications, Vol. 12, No. 6, pp. 53–64, November 1992.
A. Peleg and U. Weiser, "MMX Technology Extension to the Intel Architecture," IEEE Micro, Vol. 16, No.4, 1996, pp. 42–50.
R.L. Sites and R. Witek, Alpha AXP Architecture: Reference Manual, 2nd edn., Digital Press, Burlington, 1995.
P.M. Kogge, The Architecture of Pipelined Computers, Advanced computer science series. McGraw-Hill Book Company, New York, 1981.
R. Montoye, E. Hokenek, and S. Runyon, "Design of the IBM RISC System/6000 Floating-Point Execution Unit," IBM Journal of Research and Development, Vol. 34, No. 1, 1990, pp. 59–70.
S. Vassiliadis, J. Phillips, and B. Blaner, "Interlock Collapsing ALU's," IEEE Transactions on Computers, Vol. 42, No. 11, 1993, pp. 825–839.
F. Onion, A. Nicolau, and N. Dutt, "Compiler Feedback in ASIP Design," Technical Report 94–2, Department of Information and Computer Science, University of California, September 1994.
J.L. Mitchell, W.B. Pennebaker, C.E. Fogg, and D.J. LeGall, MPEG Video Compression Standard, Digital Multimedia Standard Series. Chapman and Hall, New York, 1996.
L. Dadda, "Some Schemes for Parallel Multipliers," Alta Frequenza, Vol. 34, 1965, pp. 349–356.
T. Boutell and T. Lane, "PNG (Portable Network Graphics) Specification," version 1.0. ftp://ftp.uu.net/graphics/png/docu-ments/ png-1.0-w3c.ps.gz.
S. Waser and M.J. Flynn, Introduction to Arithmetic for Digital Systems Designers, CBS College Publishing, 1982.
T. Doyle and P. Frencken, "Median Filtering of Television Images," in Proceedings of the International Conference on Consumer Electronics, Digest of Technical Papers, June 1986, pp. 186–187.
E.A. Hakkennes, "Multimedia Hardware Accelerators," Ph.D. Thesis, Delft University of Technology, December 1999.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Hakkennes, E., Vassiliadis, S. Multimedia Execution Hardware Accelerator. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 28, 221–234 (2001). https://doi.org/10.1023/A:1011117608815
Published:
Issue Date:
DOI: https://doi.org/10.1023/A:1011117608815