Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content

Advertisement

SpringerLink
Log in

Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware–Software Codesign

  • Published:
Design Automation for Embedded Systems Aims and scope Submit manuscript

Abstract

This paper compares three heuristic search algorithms: genetic algorithm (GA), simulated annealing (SA) and tabu search (TS), for hardware–software partitioning. The algorithms operate on functional blocks for designs represented as directed acyclic graphs, with the objective of minimising processing time under various hardware area constraints. Thecomparison involves a model for calculating processing time based on a non-increasing first-fit algorithm to schedule tasks, given that shared resource conflicts do not occur. The results show that TS is superior to SA and GA in terms of both search time and quality of solutions. In addition, we have implemented an intensification strategy in TS called penalty reward, which can further improve the quality of results.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Explore related subjects

Find the latest articles, discoveries, and news in related topics.

References

  1. Oudghiri, H., and B. Kaminska. Global Weighted Scheduling and Allocation Algorithms, In European Conference on Design Automation, pp. 491-495.

  2. Jinwoo, S., D.-I. Kang, and S. P. Crago. A Communication Scheduling Algorithm for Multi-FPGA Systems, IEEE Symposium on Field-Programmable Custom Computing Machines, 2000, pp. 299-300.

  3. Diessel, O., H. ElGindy, M. Middendorf, H. Schmeck, and B. Schmidt. Dynamic Scheduling of Tasks on Partially Reconfigurable FPGAs, Computers and Digital Techniques, IEE Proceedings, vol. 147,no. 3, pp. 181-188, May 2000.

    Google Scholar 

  4. Gerez, S. H. Algorithm for VLSI Design Automation, John Wiley & Sons, England, 1999.

    Google Scholar 

  5. Neapolitan, R., and K. Naimipour. Foundations of Algorithms using C++ Pseudo Code, 2nd ed., Jones and Bartlett Publishers, London, 1998.

    Google Scholar 

  6. Rayward-Smith, V. J., I. H. Osman, C. R. Reeves, and G. D. Smith. Modern Heuristic Search Methods, John Wiley and Sons, England 1996.

    Google Scholar 

  7. Kalavade, A., and E. A. Lee. A Global Criticality/Local Phase Driven Algorithm for the Constrained Hardware/Software Partitioning Problem, Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994, pp. 42-48.

  8. Coley, D. A. An Introduction to Genetic Algorithms for Scientists and Engineers, World Scientific, 1998.

  9. Hidalgo, J. I., and J. Lanchares. Functional Partitioning for Hardware-Software Codesign Using Genetic Algorithms, EUROMICRO 97. New Frontiers of Information Technology, Proceedings of the 23rd EUROMICRO Conference, 1997, pp. 631-638.

  10. Chatha, K. S., and R. Vemuri. An Iterative Algorithm for Partitioning and Scheduling of Area Constrained Hardware Software Systems, IEEE International Workshop on Rapid System Prototyping, 1999, pp. 134-139.

  11. Chatha, K. S., and R. Vemuri. A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems, 11th International Symposium on System Synthesis Proceedings, 1998, pp. 145-151.

  12. Bakshi, S., and D. Gajski. Partitioning and Pipelining for Performance-Constrained Hardware/Software System, IEEE Transaction on Very Large Scale Integration Systems, vol. 7,no. 4, pp. 419-432, Dec. 1999.

    Google Scholar 

  13. Chatha, K. S., and R. Vemuri. An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling, Journal of Design Automation for Embedded Systems, vol. 5, pp. 281-293, 2000.

    Google Scholar 

  14. Ernst, R., J. Henkel, and T. Benner. Hardware-Software Co-Synthesis for Micro-Controllers, IEEE Design and Test of Computer, vol. 10,no. 4, pp. 64-75, 1993.

    Google Scholar 

  15. Vahid, F., and T. Le. Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning, Journal of Design Automation for Embedded Systems, vol. 2, pp. 237-261, 1997.

    Google Scholar 

  16. Harkin, J., T. M. McGinnity, and L. P. Maguire. Partitioning Methodology for Dynamically Reconfigurable Embedded Systems, Computers and Digital Techniques, IEE Proceedings, vol. 147,no. 6, pp. 391-396, Nov. 2000

    Google Scholar 

  17. Bianco, L., M. Auguin, G. Gogniat, and A. Pegatoquet. A Path Analysis Based Partitioning for Time Constrained Embedded Systems, Proceedings of the Sixth International Workshop on Hardware/Software Codesign (CODES/CASHE'98), 1998, pp. 85-89.

  18. Maestro, J. A., D. Mozos, and H. A. Mecha. Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process, Proceedings on Design, Automation and Test in Europe, 1998, pp. 218-225.

  19. Axelsson, J. Architecture Synthesis and Partitioning of Real-Time Systems: A Comparison of Three Heuristic Search Strategies, Proceedings of the Fifth International Workshop on Hardware/Software Codesign, (CODES/CASHE'97), 1997, pp. 161-165.

  20. Gajski, D. D., F. Vahid, S. Narayau, and J. Gong. Specification and Design of Embedded System, Prentice Hall, 1994.

  21. Reeves, R., Modern Heuristic Techniques for Combinatorial Problem, Blackwell Scientific Publication, UK, 1993.

    Google Scholar 

  22. Eles, P., and Z. Peng et al. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search, Design Automation for Embedded Systems, vol. 2, pp. 5-32, 1996.

    Google Scholar 

  23. Alander, J. T. Optimal Population Size of Genetic Algorithms, Proceeding in IEEE Computer Society Press, pp. 65-70, 1992.

  24. Haynes, S. D., J. Stone, P. Y. K. Cheung, and W. Luk. Video Image Processing with the Sonic Architecture, IEEE Computer, vol. 33,no. 4, pp. 50-57, April 2000.

    Google Scholar 

  25. Kirkpatrick, S., C. D. Gelatt, Jr., and M. P. Vecchi. Optimization by Simulated Annealing, Science, vol. 200,no. 4598, pp. 671-680, 1983.

    Google Scholar 

  26. Buck, J., S. Ha, E. Lee, and D. Messerschmitt. Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems, International Journal on Computer Simulation, vol. 4, pp. 155-182, 1994.

    Google Scholar 

  27. Chou, P., and R. Ortega, and G. Borriello The Chinook Hardware/Software Co-Synthesis System, International Symposium on System Synthesis (ISSS), pp. 22-27, 1995.

  28. Teich, J., T. Blickle, and L. Thiele, An Evolutionary Approach to System-Level Synthesis, Proceedings of International Workshop on Codesign (Codes), 1997.

  29. Dick, R. P., and N. K. Jha. MOGAC: A Multiobjective Genetic Algorithm for Hardware-Software Cosynthesis of Distributed Embedded Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17,no. 10, pp. 920-935, Oct. 1998.

    Google Scholar 

  30. Sih, G. C., and E. A. Lee. A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures, IEEE Transactions on Parallel and Distributed Systems, vol. 4,no. 2, pp. 175-187, Feb. 1993.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical & Electronic Engineering, Imperial College, Exhibition Road, London

    Theerayod Wiangtong

  2. Department of Electrical & Electronic Engineering, Imperial College, Exhibition Road, London

    Peter Y. K. Cheung

  3. Department of Computing Imperial College, Queen's Gate, London

    Wayne Luk

Authors
  1. Theerayod Wiangtong
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Peter Y. K. Cheung
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Wayne Luk
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Wiangtong, T., Cheung, P.Y.K. & Luk, W. Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware–Software Codesign. Design Automation for Embedded Systems 6, 425–449 (2002). https://doi.org/10.1023/A:1016567828852

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1016567828852

Search

Navigation