Abstract
In this work we present an implementation of the exponential function in double precision, in a unit that supports IEEE floating-point arithmetic. As existing proposals, the implementation is based on the use of a floating-point multiplier and additional hardware. We decompose the computation into three subexponentials. The first and third subexponentials are computed in a conventional way (table look-up and polynomial approximation). The second subexponential is computed based on a transformation of the slow radix-2 digit-recurrence algorithm into a fast computation by using the multiplier and additional hardware. We present a design process that permits the selection of the most convenient trade-off between hardware complexity and latency. We discuss the algorithm, the implementation, and perform a rough comparison with three proposed designs. Our estimations indicate that the implementation proposed in this work presents better trade-off between hardware complexity and latency than the compared designs.
Similar content being viewed by others
References
T. Lynch, A. Ahmed, and M. Schulte, “The K5 Transcendental Functions,” in Proc.12th IEEE Symposium on Computer Arithmetic, 1995, pp. 163–170.
J.M. Muller, Elementary Functions: Algorithms and Implementations, Birkhauser, 1997.
D.B. Papworth, “Tunning the Pentium Pro Microarchitecture,” IEEE Micro, vol. 16, 1996, pp. 8–15.
S. Story and P.T.P. Tang, “New Algorithms for Improved Transcendental Functions on IA-64,” in Proc.14th IEEE Symposium on Computer Arithmetic, 1999, pp. 4–11.
J. Harrison, T. Kubaska, S. Story, and P.T.P. Tang, “The Computation of Transcendental Functions on the IA-64 Architecture,” Intel Technology Journal, Q4, 1999.
M. Schulte and E. Swartzlander, “Exact Rounding of Certain Elementary Functions,” in Proc.11th IEEE Symposium on Computer Arithmetic, 1993, pp. 138–145.
W.F. Wong and E. Goto, “Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers,” IEEE Transactions on Computers, vol. 43, no. 3, 1994.
J.C. Bajard, S. Kla, and J.M. Muller, “BKM: A New Hardware Algorithm for Complex Elementary Functions,” IEEE Transactions on Computers, vol. 4, 1994, pp. 955–96.
R.C. Chen, “Automatic Computation of Exponentials, Logarithms, Ratios and Square Roots,” IBM J.Res.Dev., vol. 16, 1972, pp. 380–388.
V. Kantabutra, “On Hardware for Computing Exponential and Trigonometric Functions,” IEEE Transactions on Computers, vol. 45, no. 3, 1996, pp. 328–339.
W.H. Specker, “A Class of Algorithms for ln(x), exp(x), sin(x), cos(x), tan-1(x) and cot-1(x),” IEEE Trans.Electronic Computers, vol. 14, 1965, pp. 85–86.
M.D. Ercegovac, “Radix-16 Evaluation of Certain Elementary Functions,” IEEE Trans.on Comput., vol. C-22, 1973, pp. 561–566.
P.W. Baker, “Parallel Multiplicative Algorithms for Some Elementary Functions,” IEEE Trans.on Comput., vol. 3, 1975, pp. 322–325.
E. Antelo, J.D. Bruguera, T. Lang, J. Villalba, and E.L. Zapata, “High-Radix CORDIC Rotation Based on Selection by Rounding,” in Lecture Notes in Computer Science (EUROPAR-96: Par-allel Processing, Worshop: Parallel Image/Video Processing and Computer Arithmetic), vol. 1124, 1996, pp. 155–164.
P.T. Tang, “Table-Lookup Algorithms for Elementary Functions and Their Error Analysis,” in Proc.10th IEEE Symposium on Computer Arithmetic, 1991, pp. 232–236.
V.K. Jain and L. Lin, “High-Speed Double Precision Computation of Nonlinear Functions,” in Proc.12th IEEE Symposium on Computer Arithmetic, 1995, pp. 107–114.
M.D. Ercegovac, T. Lang, J.-M. Muller, and A. Tisserand, “Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers,” IEEE Transactions on Computers, vol. 49, no. 7, 2000, pp. 628–637.
I. Koren and O. Zinaty, “Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations,” IEEE Transactions on Computers, vol. 39, no. 8, 1990, pp. 1030–1037.
A. Vázquez and E. Antelo, “Implementation of the Exponential Function in a Floating-Point Unit,” Internal Report. Dept. Electrónica y Computación, University of Santiago de Com-postela, Spain, October 2000.
P.W. Baker, “Suggestion for a Fast Binary Sine/Cosine Generator,” IEEE Transactions on Computers, vol. 25, 1976, pp. 1134–1136.
A. Ziv, “Fast Evaluation of Elementary Mathematical Functions with Correctly Rounded Last Bit,” ACM Transactions on Mathematical Software, vol. 17, 1991, pp. 410–423.
M.J. Schulte and J.E. Stine, “Approximating Elementary Functions with Symmetric Bipartite Tables,” IEEE Trans.on Computers, vol. 48, no. 8, 1999, pp. 842–847.
G. Gerwig and M. Kroener, “Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow,” in Proc.14th IEEE Symposium on Computer Arithmetic, 1999, pp. 266–273.
R.K. Yu and G.B. Zyner, “167 MHzRadix-4 Floating-Point Multiplier,” in Proc.12th IEEE Symposium on Computer Arithmetic, 1995, pp. 149–154.
T. Horel and G. Lauterbach, “UltraSPARC-III: Designing Third-Generation 64-bit Performance,” IEEE Micro, vol. 19, 1999, pp. 73–85.
A. Naini, A. Dhablania, W. James, and D. Das Sarma, “1-GHz HAL SPARC64 Dual Floating-Point Unit with RAS Features,” in Proc.15th IEEE Symposium on Computer Arithmetic, 2001, pp. 173–183.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Vázquez, Á., Antelo, E. Implementation of the Exponential Function in a Floating-Point Unit. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 33, 125–145 (2003). https://doi.org/10.1023/A:1021102104078
Published:
Issue Date:
DOI: https://doi.org/10.1023/A:1021102104078