Abstract
The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage and low cost. This paper describes an important fault class, called dynamic faults, that cannot be ignored anymore. The dynamic fault behavior can take place in the absence of the static fault behavior, for which the conventional memory tests have been constructed. The concept of dynamic fault will be established and validated for both dynamic and static Random-Access-Memories. A systematic way to develop fault models for dynamic faults will be introduced. Further, it will be shown that conventional memory tests do not necessarily detect its dynamic faulty behavior, which has been shown to exist in real designs. The paper therefore also presents new memory tests to target the dynamic fault class.
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References
M.S. Abadir and J.K. Reghbati, “Functional Testing of Semiconductor Random Access Memories,” ACMComputer Surveys, vol. 15, no. 3, pp. 175-198, 1983.
R.D. Adams and E.S. Cooley, “Analysis of a Deceptive Read Destructive Memory Fault Model and Recommended Testing,” in Proc. IEEE North Atlantic Test Workshop, 1996.
Z. Al-Ars and Ad J. van de Goor, “Impact of Memory Cell Array Bridges on the Faulty Behavior in Embedded DRAMs,” in Proc. of Asian Test Symposium, 2000, pp. 282-289.
Z. Al-Ars and Ad J. van de Goor, “Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs,” in Proc. of Design Automation and Test in Europe, 2001, pp. 496-503.
Z. Al-Ars and A.J. van de Goor, “Approximating Infinite Dynamic Behavior for DRAM Cell Defects,” in Proc. IEEE VLSI Test Symp., 2002, pp. 401-406.
M.A. Breuer and A.D. Friedman, Diagnosis and Reliable Design of Digital Systems, Woodland Hills, CA: Computer Science Press, 1976.
J.H. De Jonge and A.J. Smeulders, “Moving Inversions Test Pattern is Thorough, Yet Speedy,” in Comp. Design, 1976, pp. 169-173.
R. Dekker et al., “A Realistic Fault Model and Test Algorithms for Static Random Access Memories,” IEEE Trans. on Computers,vol. C9, no. 6, pp. 567-572, 1990.
S. Hamdioui and A.J. van de Goor, “Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests,” in Proc. of Asian Test Symposium, Taipei, Taiwan, 2000, pp. 131-138.
S. Hamdioui and A.J. van de Goor, “Thorough Testing of any Multi-Port Memory with Linear Tests,” In IEEE Trans. on CAD, vol. 21, no. 2, pp. 217-231, Feb. 2002.
S. Hamdioui and A.J. van de Goor, “Efficient Tests for Realistic Faults in Dual-Port SRAMs,” in IEEE Trans. on Computers, vol. 51, no. 5, pp. 460-473, May 2002.
S. Hamdioui, A.J. van de Goor, and M. Rodgers, “March SS: A Test for All Static Simple RAM Faults,” in Proc. of IEEE International Workshop on Memory Technology, Design and Test, 2002, pp. 95-100.
S. Hamdioui, Z. Al-ars, and A.J. van de Goor, “Testing Static and Dynamic Faults in Random Access Memories,” in Proc. of IEEE VLSI Test Symposium, 2002, pp. 395-400.
W. Huott et al., “The Attack of the ‘Holey Shmoos’: A Case of the Advanced DFD and Picosecond Imaging Circuit Analysis (PICA),” in Proc. of IEEE International Test Conference,1999, pp. 883-891.
M. Inoue et al., “A New Test Evaluation Chip for Lower Cost Memory Tests,” IEEE Design and Test of Computers, vol. 10, no. 1, pp. 15-19, March 1993.
V.K. Kim and T. Chen, “On Comparing Functional Fault Coverage and Defect Coverage for Memory Testing,” IEEE Trans. on CAD, vol. 18, no. 11, pp. 1676-1683, 1999.
M. Marinescu, “Simple and Efficient Algorithms for Functional RAM Testing,” in Proc. of IEEE International Test Conference, 1982, pp. 236-239.
S. Naik et al., “Failure Analysis of High Density CMOS SRAMs,” IEEE Design and Test of Computers, vol. 10, no. 1, pp. 13-23, June 1993.
R. Nair, “An Optimal Algorithm for Testing Stuck-at Faults Random Access Memories,” IEEE Trans. on Computers, vol. C-28, no. 3, pp. 258-261, 1979.
C.A. Papachristou and N.B. Saghal, “An Improved Method for Detecting Functional Faults in Random Access Memories,” IEEE Trans. on Computers,vol. C-34, no. 3, pp. 110-116, 1985.
I. Schanstra and A.J. van de Goor, “Industrial Evaluation of Stress Combinations for March Tests Applied to SRAMs,” in Proc. IEEE Int. Test Conference, 1999, pp. 983-992.
D.S. Suk and S.M. Reddy, “A March Test for Functional Faults in Semiconductor Random-Access Memories,” IEEE Trans. on Computers, vol. C30, no. 12, pp. 982-985, 1981.
A.J. van de Goor, Testing Semiconductor Memories, Theory and Practice, ComTex Publishing, Gouda: The Netherlands, 1998. Web: http://cardit.et.tudelft.nl/~vdgoor
A.J. van de Goor and Z. Al-Ars, “Functional Fault Models: A Formal Notation and Taxonomy,” in Proc. of IEEE VLSI Test Symposium, 2000, pp. 281-289.
A.J. van de Goor and J. de Neef, “Industrial Evaluation of DRAMs Tests,” in Proc. of Design Automation and Test in Europe, March 1999, pp. 623-630.
A.J. van de Goor and G. Gaydadjiev, “March LR: A Memory Test for Realistic Linked Faults,” in Proc. IEEE VLSI Test Symposium, 1996, pp. 272-280.
A.J. van de Goor and G.N. Gayadadjiev, “March U: A Test for All Unlinked Memory Faults,” IEE Proc. of Circuits Devices and Systems, vol. 144, no. 3, pp. 155-160, 1997.
A.J. van de Goor et al., “March LA: A Test for Linked Memory Faults,” in Proc. of European Design and Test Conf., 1999, p. 627.
P.K. Veenstra et al., “Testing of Random Access Memories: Theory and Practice,” IEE Proc. of Circuits, Devices, and Systems, vol. 135, no. 1, pp. 24–28, 1988.
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Hamdioui, S., Al-Ars, Z., van de Goor, A.J. et al. Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests. Journal of Electronic Testing 19, 195–205 (2003). https://doi.org/10.1023/A:1022802010738
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DOI: https://doi.org/10.1023/A:1022802010738