IEICE Trans - Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance

Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance

Atsushi KUROKAWA
Masanori HASHIMOTO
Akira KASEBE
Zhangcai HUANG
Yun YANG
Yasuaki INOUE
Ryosuke INAGAKI
Hiroo MASUDA

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E88-A No.12 pp.3453-3462
Publication Date: 2005/12/01
Online ISSN:
DOI: 10.1093/ietfec/e88-a.12.3453
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword:
capacitance formula, capacitance calculation, capacitance extraction, interconnect capacitance,

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Summary:
Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

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