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Voltage-Tunable Quantum-Dot Array by Patterned Ge-Nanowire-Based Metal-Oxide-Semiconductor Devices

Subhrajit Sikdar, Basudev Nag Chowdhury, Rajib Saha, and Sanatan Chattopadhyay
Phys. Rev. Applied 15, 054060 – Published 26 May 2021
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  • INTRODUCTION
  • SCHEME OF NWMOS-BASED VTQDs
  • FABRICATION AND CHARACTERIZATION
  • CAPACITANCE MEASUREMENTS
  • THEORETICAL MODELING
  • CONCLUSION
  • ACKNOWLEDGMENTS
    • Supplemental Material
    References

    Abstract

    We report the fabrication of an array of highly scaled Ge-nanowire-based (radius ∼ 25 nm) vertical metal-oxide-semiconductor devices that can operate as voltage-tunable quantum dots (VTQDs) at room temperature. The electrons in such nanowires experience geometrical confinement in the radial direction, whereas they can be confined axially by tuning the applied bias to manipulate the quantum states. Such three-dimensional confinement of electrons is confirmed from the steplike responses in the room-temperature capacitance-voltage (C-V) characteristics at relatively low frequency (200 kHz). Each step is observed to encompass convolution of the quantized states occupying about six electronic charges. Such ultrasmall capacitance (∼aF) is measured by exploring a technique that utilizes the method of removing frequency dispersion. Details of such carrier confinement are analyzed in the current work by theoretically modeling the device’s transport properties based on the nonequilibrium Green function formalism.

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    • Received 8 January 2021
    • Revised 8 April 2021
    • Accepted 11 May 2021

    DOI:https://doi.org/10.1103/PhysRevApplied.15.054060

    © 2021 American Physical Society

    Physics Subject Headings (PhySH)

    1. Research Areas
    Capacitance
    1. Physical Systems
    DevicesElemental semiconductorsNanowiresQuantum dots
    1. Techniques
    LithographyNonequilibrium Green's functionScanning electron microscopy
    Condensed Matter, Materials & Applied Physics

    Authors & Affiliations

    Subhrajit Sikdar1, Basudev Nag Chowdhury1, Rajib Saha1, and Sanatan Chattopadhyay1,2,*

    • 1Department of Electronic Science, University of Calcutta, Kolkata, India
    • 2Centre for Research in Nanoscience and Nanotechnology (CRNN), University of Calcutta, Kolkata, India

    • *scelc@caluniv.ac.in

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    Vol. 15, Iss. 5 — May 2021

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    Images

    • Figure 1
      Figure 1

      (a) Schematic of Ge-nanowire-based MOS device on Si substrate, indicating the formation of VTQDs near the Ge NW/SiO2 interface due to the combined effect of structural and electrical confinement along radial and longitudinal directions, respectively. (b) Energy-band diagram of the NWMOS device under unbiased conditions, illustrating Si and Ge valence- and conduction-band offsets. (c) Energy-band diagram for positive bias applied on the metal, depicting regions of 3D-confined electrons and 2D-confined holes, along with their respective local density of states; 3D-confined electrons form VTQDs.

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    • Figure 2
      Figure 2

      (a) FESEM image of Pt/SiO2/Ge NW vertical MOS device, indicating the formation of voltage-tunable quantum dot region on top of Ge nanowires beneath the oxide-semiconductor interface. Image is captured at a magnification of 120 × 103 times and extra high tension of 3 kV. FESEM images of the array of NWMOS-based VTQD devices with inter-nanowire spacings of (b) about 150 nm, (c) about 200 nm, and (d) about 250 nm. Such devices are patterned using an electron dose of 65k µc/cm2. Nanowire radii for all cases are about 25 nm (distribution of nanowire radii is given in Ref. [22]).

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    • Figure 3
      Figure 3

      (a) TEM image of single-nanowire MOS, showing Ge (semiconductor), SiO2 (oxide), and Pt (metal) regions, where nanowire radius and thickness of oxide material are observed to be about 25 and 20 nm respectively. (b) SAED pattern of Ge nanowire, showing a ring with bright spots, corresponding to the [200] plane of Ge. (c) Results of EDX measurements performed in situ under TEM, along with atomic and weight percentages of relevant materials. (d) Plot of XRD profile of patterned NWMOS, confirming Ge [400] plane at 2θ = 62.6° on [400] plane of Si substrate.

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    • Figure 4
      Figure 4

      (a) Plot of C-V characteristics measured in situ under FESEM at room temperature for 200 kHz and 1 MHz frequencies, showing accumulation-to-inversion region. Low-frequency response of C-V curve exhibits steplike nature, indicating 3D confinement of electrons with about 6e per volt per step in the VTQD formation region. Humps created due to interface traps and hole (light-heavy) confinement are also shown. (b) Theoretical plot of C-V characteristics of single-nanowire MOS device of identical dimensions obtained from the analytical model based on NEGF formalism. In such a plot, contributions of different carriers (heavy holes, light holes, and electrons) in the net capacitance behavior are shown along with experimental results.

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    • Figure 5
      Figure 5

      Plots of local density of states in energy space with distance from oxide-semiconductor interface for 3D-confined electrons and 2D-confined holes: (a) heavy holes and (b) light holes. Applied voltage at the metal terminal is considered to be 3 V. Results are obtained from NEGF-based analytical model developed in the current work. LDOS for electrons show spikes for created 3D-confined discrete states in the voltage-tunable quantum-well region, whereas such LDOS for holes are broadened due to their free longitudinal motion towards the substrate. Such broadening is observed to depend significantly on hole effective-mass (i.e., light-heavy hole) mismatch between Si and Ge.

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