A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V<formula formulatype="inline"><tex Notation="TeX">$_{\rm TH}$</tex></formula> Read-Port, and Offset Cell VDD Biasing Techniques

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V- Read-Port, and Offset Cell VDD Biasing Techniques | IEEE Journals & Magazine | IEEE Xplore

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