Article

Scaling of stack effect and its application for leakage reduction

Authors:

Siva Narendra,

Vivek De,

Dimitri Antoniadis,

Anantha Chandrakasan,

Shekhar BorkarAuthors Info & Claims

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

Pages 195 - 200

https://doi.org/10.1145/383082.383132

Published: 06 August 2001 Publication History

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Cited By

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Garzón EHanhan RLanuzza MTeman AYavits L(2024)FASTA: Revisiting Fully Associative Memories in Computer MicroarchitectureIEEE Access10.1109/ACCESS.2024.335596112(13923-13943)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3355961
Li PZhu SXi WXu CZheng DHuang K(2023)Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS TechnologyApplied Sciences10.3390/app1306347113:6(3471)Online publication date: 8-Mar-2023
https://doi.org/10.3390/app13063471
Li YZhao JLiu YWang G(2023)A Comprehensive Study on the Design Methodology of Level Shifter CircuitsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.321398170:1(302-314)Online publication date: Jan-2023
https://doi.org/10.1109/TCSI.2022.3213981
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Index Terms

Scaling of stack effect and its application for leakage reduction
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Signal processing systems
  2. Integrated circuits
2. Information systems
  1. Data management systems
    1. Data structures
      1. Data layout
        Data compression

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Published In

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

August 2001

393 pages

ISBN:1581133715

DOI:10.1145/383082

Chairmen:
Enrico Macii
Politecnico di Torino, Turin, Italy
,
Vivek De
Intel Corporation, Hillsboro, OR
,
Mary Jane Irwin
Penn State Univ., University Park

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 August 2001

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ISLPED01: International Symposium on Low Power Electronics and Design

California, Huntington Beach, USA

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ISLPED '01 Paper Acceptance Rate 73 of 194 submissions, 38%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Garzón EHanhan RLanuzza MTeman AYavits L(2024)FASTA: Revisiting Fully Associative Memories in Computer MicroarchitectureIEEE Access10.1109/ACCESS.2024.335596112(13923-13943)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3355961
Li PZhu SXi WXu CZheng DHuang K(2023)Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS TechnologyApplied Sciences10.3390/app1306347113:6(3471)Online publication date: 8-Mar-2023
https://doi.org/10.3390/app13063471
Li YZhao JLiu YWang G(2023)A Comprehensive Study on the Design Methodology of Level Shifter CircuitsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.321398170:1(302-314)Online publication date: Jan-2023
https://doi.org/10.1109/TCSI.2022.3213981
Deng LLi KShan W(2023)IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits2023 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS46773.2023.10182138(1-5)Online publication date: 21-May-2023
https://doi.org/10.1109/ISCAS46773.2023.10182138
Kamalkumar VSingh R(2023)Design and Development of Low Power and Area Efficient Design for VLSI Circuits2023 4th International Conference on Smart Electronics and Communication (ICOSEC)10.1109/ICOSEC58147.2023.10276181(108-111)Online publication date: 20-Sep-2023
https://doi.org/10.1109/ICOSEC58147.2023.10276181
Mittal D(2023)SRAM Cell Leakage Reduction Methodologies for Low Leakage Cache Memories2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT)10.1109/ICCCNT56998.2023.10308241(1-5)Online publication date: 6-Jul-2023
https://doi.org/10.1109/ICCCNT56998.2023.10308241
Mittal D(2023)Design a Gated PMOS Spillage Reduction Approach for CMOS SRAM Cell in 90nm Technology Node2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT)10.1109/ICCCNT56998.2023.10307843(1-4)Online publication date: 6-Jul-2023
https://doi.org/10.1109/ICCCNT56998.2023.10307843
Gupta TPandey APandey D(2023)Influence of Gate Oxide and Subthreshold Leakage in Domino Using Si Nano-MaterialsSilicon10.1007/s12633-023-02555-815:16(6901-6910)Online publication date: 16-Jun-2023
https://doi.org/10.1007/s12633-023-02555-8
Coulon JLiu J(2022)A Diode-Based D-2D DAC Architecture with Leakage Current Compensation for Ultra-low Power Application2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937958(1445-1448)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937958
Mittal D(2022)6T SRAM Cell Design Using CMOS at Different Technology nodes2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)10.1109/GCAT55367.2022.9972192(01-05)Online publication date: 7-Oct-2022
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