research-article

WireMap: FPGA technology mapping for improved routability

Authors:

Alan MishchenkoAuthors Info & Claims

FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays

Pages 47 - 55

https://doi.org/10.1145/1344671.1344680

Published: 24 February 2008 Publication History

Abstract

This paper presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the iterative mapping optimization to reduce the total number of pin-to-pin connections (or edges). The average edge reduction of 9.3% is achieved while maintaining depth and LUT count of state-of-the-art technology mapping. Placing and routing the resulting netlists leads to an 8.5% reduction in the total wire length, a 6.0% reduction in minimum channel width, and a 2.3% reduction in critical path delay. Applying WireMap has an additional advantage of reducing an average number of inputs of LUTs without increasing the total LUT count and depth. The percentages of 5- and 6-LUTs in a typical design are reduced, while the percentages of 2-, 3-, and 4-LUTs are increased. These smaller LUTs can be merged into pairs and implemented using the dual output LUT structure found in commercial FPGAs. WireMap leads to 9.4% fewer dual-output LUTs after merging

References

[1]

Altera. Stratix III Device Handbook, http://www.altera.com/literature/hb/stx3/stratix3_handbook.pdf

[2]

Altera. "Improving FPGA performance and area using an adaptive logic module", http://www.altera.com/literature/cp/cp-01004.pdf

[3]

Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, Release 61225. http://www.eecs.berkeley.edu/~alanmi/abc/

[4]

V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for deep-submicron FPGAs, Kluwer Academic Publishers, 1999, ISBN 0-7923-8460-1.

Digital Library

[5]

S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam, "Reducing structural bias in technology mapping", Proc. ICCAD '05, pp. 519--526.

Digital Library

[6]

D. Chen and J. Cong. "DAOmap: A depth-optimal area optimization mapping algorithm for FPGA designs," Proc. ICCAD'04, pp. 752--757.

Digital Library

[7]

J. Cong and Y. Ding, "FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs", IEEE TCAD, Vol. 13(1), Jan. 1994, pp. 1--12.

Digital Library

[8]

J. Cong, C. Wu, and Y. Ding, "Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution," Proc. FPGA'99, pp. 29--36.

Digital Library

[9]

S. Gupta, A. Anderson, L. Farragher, and Q. Wang. "CAD techniques for power optimization in Virtex-5 FPGAs", to appear in Proc. Custom Integrated Circuits Conference, 2007.

[10]

E. Lehman, Y. Watanabe, J. Grodstein, and H. Harkness, "Logic decomposition during technology mapping," IEEE Trans. CAD, vol. 16(8), 1997, pp. 813--833.

Digital Library

[11]

V. Manohara-rajah, S. D. Brown, and Z. G. Vranesic, "Heuristics for area minimization in LUT-based FPGA technology mapping," Proc. IWLS '04, pp. 14--21.

[12]

A. Mishchenko, S. Chatterjee, and R. Brayton, "Improvements to technology mapping for LUT-based FPGAs", Proc. FPGA '06, pp. 41--49.

Digital Library

[13]

A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-aware AIG rewriting: A fresh look at combinational logic synthesis", Proc. DAC'06, pp. 532--536.

Digital Library

[14]

A. Mishchenko, R. Brayton, J.-H. R. Jiang, and S. Jang, "SAT-based logic optimization and resynthesis", Proc. IWLS '07, pp. 358--364.

[15]

A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, "Combinational and sequential mapping with priority cuts", Proc. ICCAD '07.

Digital Library

[16]

R. Murgai, Y. Nishizaki, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Logic synthesis for programmable gate arrays", Proc. DAC'90, pp. 620--625.

Digital Library

[17]

P. Pan and C.-C. Lin, "A new retiming-based technology mapping algorithm for LUT-based FPGAs," Proc. FPGA '98, pp. 35--42.

Digital Library

[18]

E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. "SIS: A System for Sequential Circuit Synthesis". Memorandum No. UCB/ERL M92/41, Department of EECS. UC Berkeley, May 1992.

[19]

Xilinx White Paper. "Achieving higher system performance with the Virtex--5 family of FPGAs", http://direct.xilinx.com/bvdocs/whitepapers/wp245.pdf

Cited By

Yazdanshenas SBetz V(2017)Automatic circuit design and modelling for heterogeneous FPGAs2017 International Conference on Field Programmable Technology (ICFPT)10.1109/FPT.2017.8280115(9-16)Online publication date: Dec-2017
https://doi.org/10.1109/FPT.2017.8280115
Anderson JWang QRavishankar C(2012)Raising FPGA Logic Density Through Synthesis-Inspired ArchitectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.210278120:3(537-550)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1109/TVLSI.2010.2102781
Anderson JWang Q(2011)Area-efficient FPGA logic elementsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950894(369-375)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950894
Show More Cited By

Index Terms

WireMap: FPGA technology mapping for improved routability
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
  2. Very large scale integration design
    1. Application-specific VLSI designs

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cover image ACM Conferences

FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays

February 2008

278 pages

ISBN:9781595939340

DOI:10.1145/1344671

General Chair:
Mike Hutton
Altera, USA
,
Program Chair:
Paul Chow
University of Toronto, Canada

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 24 February 2008

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FPGA08

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FPGA08: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 24 - 26, 2008

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Yazdanshenas SBetz V(2017)Automatic circuit design and modelling for heterogeneous FPGAs2017 International Conference on Field Programmable Technology (ICFPT)10.1109/FPT.2017.8280115(9-16)Online publication date: Dec-2017
https://doi.org/10.1109/FPT.2017.8280115
Anderson JWang QRavishankar C(2012)Raising FPGA Logic Density Through Synthesis-Inspired ArchitectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.210278120:3(537-550)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1109/TVLSI.2010.2102781
Anderson JWang Q(2011)Area-efficient FPGA logic elementsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950894(369-375)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950894
Kennings AVorwerk KKundu APevzner VFox A(2011)FPGA technology mapping with encoded libraries and staged priority cutsACM Transactions on Reconfigurable Technology and Systems10.1145/2068716.20687214:4(1-17)Online publication date: 28-Dec-2011
https://dl.acm.org/doi/10.1145/2068716.2068721
Luu JAnderson JRose JWawrzynek JCompton K(2011)Architecture description and packing for logic blocks with hierarchy, modes and complex interconnectProceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1950413.1950457(227-236)Online publication date: 27-Feb-2011
https://dl.acm.org/doi/10.1145/1950413.1950457
Chen WZhang XYoshimura TNakamura Y(2011)A low power technology mapping method for Adaptive Logic Module2011 International Conference on Field-Programmable Technology10.1109/FPT.2011.6132674(1-5)Online publication date: Dec-2011
https://doi.org/10.1109/FPT.2011.6132674
Anderson JWang Q(2011)Area-efficient FPGA logic elements: Architecture and synthesis16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)10.1109/ASPDAC.2011.5722215(369-375)Online publication date: Jan-2011
https://doi.org/10.1109/ASPDAC.2011.5722215
Lee JHu YMajumdar RHe LLi MLin Y(2010)Fault-tolerant resynthesis with dual-output LUTsProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899791(325-330)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899791
Lee JHu YMajumdar RHe LMinming Li (2010)Fault-tolerant resynthesis with dual-output LUTs2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419873(325-330)Online publication date: Jan-2010
https://doi.org/10.1109/ASPDAC.2010.5419873
Brayton RMishchenko A(2010)ABCProceedings of the 22nd international conference on Computer Aided Verification10.1007/978-3-642-14295-6_5(24-40)Online publication date: 15-Jul-2010
https://dl.acm.org/doi/10.1007/978-3-642-14295-6_5
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