Low level scheduling using the hierarchical task graph

This paper introduces a new efficient instruction scheduling algorithm that can schedule across basic blocks. Scheduling globally, across basic blocks, is done by using an extension of the control flow graph (CFG) that combines both data and control dependence constraints. It organizes control flow into a hierarchy of dags and includes dataflow edges that cross basic blocks. We assume a type of extended CFG called the hierarchical task graph (HTG). Previously, the HTG has been used to describe the functional parallelism of programs at medium or higher levels of parallelism. Here we use the HTG to assist in finding parallelism at the instruction level. The new generation of superscalar RISC chips must keep their pipelines full and maximize multiple issue for maximum performance. This means that scheduling across basic blocks is becoming increasingly important. The HTG data structure simplifies the task of scheduling instructions across basic blocks.