research-article

A framework for early and systematic evaluation of design rules

Authors:

Rani S. Ghaida,

Puneet GuptaAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 615 - 622

https://doi.org/10.1145/1687399.1687513

Published: 02 November 2009 Publication History

Abstract

Design rules have been the primary contract between technology and design and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. Due to the focus on co-exploration in early stages of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). The framework is used to efficiently co-evaluate several debatable rules (evaluation for a 104-cell library takes 20 minutes). Results show that: a) diffusion-rounding mainly from diffusion power-straps is a dominant source of variability, b) cell-area overhead of fixed gate-pitch implementation compared to 1D-poly implementation is tolerable (5%) given the improvement in variability, and c) 1D-poly restriction, which improves manufacturability and variability, has almost no area overhead compared to 2D-poly. In addition, we explore gate-spacing rules using our evaluation framework. This exploration yields almost identical values as those of a commercial 65nm process, which serves as a validation for our approach.

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Cited By

Alam ILi TBrock SGupta P(2023)DRDebug: Automated Design Rule DebuggingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317472242:2(606-615)Online publication date: Feb-2023
https://doi.org/10.1109/TCAD.2022.3174722
Guha Neogi TJain NVerma PPermana DLutich AWeishbuch FWehella-Gamage DRamadout BVangara GKim JHerrmann TSun KBabich KPritchard DRashed M(2017)Design space analysis of novel interconnect constructs for 22nm FDX technologyDesign-Process-Technology Co-optimization for Manufacturability XI10.1117/12.2258668(101480Z)Online publication date: 17-Mar-2017
https://doi.org/10.1117/12.2258668
Leung GWang SPan AGupta PChui C(2016)An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI CircuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.247728224:5(1858-1870)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2477282
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Index Terms

A framework for early and systematic evaluation of design rules
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Hardware validation

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cover image ACM Conferences

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
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IEEE Council on Electronic Design Automation (CEDA)

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Published: 02 November 2009

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November 2 - 5, 2009

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Cited By

Alam ILi TBrock SGupta P(2023)DRDebug: Automated Design Rule DebuggingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317472242:2(606-615)Online publication date: Feb-2023
https://doi.org/10.1109/TCAD.2022.3174722
Guha Neogi TJain NVerma PPermana DLutich AWeishbuch FWehella-Gamage DRamadout BVangara GKim JHerrmann TSun KBabich KPritchard DRashed M(2017)Design space analysis of novel interconnect constructs for 22nm FDX technologyDesign-Process-Technology Co-optimization for Manufacturability XI10.1117/12.2258668(101480Z)Online publication date: 17-Mar-2017
https://doi.org/10.1117/12.2258668
Leung GWang SPan AGupta PChui C(2016)An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI CircuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.247728224:5(1858-1870)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2477282
Su PLi Y(2014)Design optimization of 16-nm bulk FinFET technology via geometric programming2014 International Workshop on Computational Electronics (IWCE)10.1109/IWCE.2014.6865878(1-4)Online publication date: Jun-2014
https://doi.org/10.1109/IWCE.2014.6865878
Cui TXie QWang YNazarian SPedram M(2014)7nm FinFET standard cell layout characterization and power density prediction in near- and super-threshold voltage regimesInternational Green Computing Conference10.1109/IGCC.2014.7039170(1-7)Online publication date: Nov-2014
https://doi.org/10.1109/IGCC.2014.7039170
Ghaida RSahu TKulkarni PGupta PHu A(2012)A methodology for the early exploration of design rules for multiple-patterning technologiesProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429395(50-56)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429395
Ghaida RGupta P(2012)DREIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.219247731:9(1379-1392)Online publication date: 1-Sep-2012
https://dl.acm.org/doi/10.1109/TCAD.2012.2192477
Park CPan DLucas K(2011)Exploration of VLSI CAD researches for early design rule evaluationProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950901(405-406)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950901
Chen XZhu JWawrzynek JCompton K(2011)Regular fabric for regular FPGA (abstract only)Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1950413.1950484(284-284)Online publication date: 27-Feb-2011
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Ghaida RTorres GGupta P(2011)Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay ControlIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2010.207630524:1(93-103)Online publication date: Feb-2011
https://doi.org/10.1109/TSM.2010.2076305
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