Application of 3-D ICs to FPGAs

FPGAs are considered to be very productive design vehicles as they allow users to iterate and converge on their designs quickly. On the other hand they are expensive, power hungry and not suitable for volume applications. This talk presents how Tierlogic Inc. applied 3D-IC fabrication techniques to come up with a solution to this problem.

The overhead in an FPGA that enables programmability is huge and consists of the area dedicated for configuration memory and muxing. Moving the configuration memory of FPGA's to a third dimension enables the cost, power and performance of the device to be improved. By separating the configuration memory from the rest of the chip it can be replaced with a single metal mask at any time, resulting in an ASIC suitable for volume production without changing the design characteristics at all. The configuration SRAMs are built using thin film transistors (TFT) on top of silicon metal layers. The talk will touch on the drivers behind using TFT for this application and challenges encountered when building these SRAMs. These devices have been fabricated in a production fab and proven to work as anticipated with high yields. Moving the configuration up and optimizing the architecture for a 3-D FPGA results in an area reduction close to 3X.

The future roadmap of the company includes improving the mobility of TFT transistors by several orders of magnitude, which would enable the muxing overhead in the FPGA to be moved into another tier as well. At this point one can anticipate a programmable device close to the cost, performance and power characteristics of a structured array.

This talk concludes with a challenge to researchers to extend the idea of transistor "tiering" to other applications and to solve the attendant interconnection problems in the vertical dimension.