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Functional multiple-output decomposition: theory and an implicit algorithm

Authors:

Bernd Wurth,

Klaus Eckl,

Kurt AntreichAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 54 - 59

https://doi.org/10.1145/217474.217506

Published: 01 January 1995 Publication History

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References

[1]

R. K. Brayton, R. L. Rudell, and A. L. Sangiovanni-Vincentelli, "MIS: A Multiple-Level Logic Optimization System," IEEE Transactions on Computer-Aided Design, vol. 6, no. 6, pp. 1062-1081, 1987.

Digital Library

Google Scholar

[2]

R. L. Ashenhurst, "The Decomposition of Switching Functions," Ann. Computation Lab. of Harvard Univ., vol. 29, pp. 74-116, 1959.

Google Scholar

[3]

J. P. Roth and R. M. Karp, "Minimization Over Boolean Graphs," IBM Journal, pp. 227-238, 1962.

Google Scholar

[4]

R. M. Karp, "Functional Decomposition and Switching Circuit Design," J. Soc. Indust. AppI. Math., vol. 11, no. 2, pp. 291- 335, 1963.

Crossref

Google Scholar

[5]

R. Murgai, Y. Nishizaki, N. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Logic Synthesis for Programmable Gate Arrays," 27th A CM/IEEE Design Automation Conference, DAC, pp. 620-625, June 1990.

Digital Library

Google Scholar

[6]

Y. Lai, M. Pedram, and S. Vrudhula, "BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis," 30th A CM/IEEE Design Automation Conference, DA C, pp. 642-647, June 1993.

Digital Library

Google Scholar

[7]

Y.-T. Lai, K.-R. R. Pan, M. Pedram, and S. Sastry, "FGMap: A Technology Mapping Algorithm for Look-Up Table Type FP- GAs Based on Function Graphs," Workshop Notes InternationaI Workshop on Logic Synthesis IWLS, pp. 961 -964, May 1993.

Google Scholar

[8]

T. Sasao, Logic Synthesis and Optimization. Boston/ London / Dordrecht: Kluwer Academic Publishers, 1993.

Digital Library

Google Scholar

[9]

R. Murgai, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Optimum Functional Decomposition Using Encoding," 31th A CM/IEEE Design Automation Conference, DAC, pp. 408- 414, 1994.

Digital Library

Google Scholar

[10]

Y.-T. Lai, K.-R. R. Pan, and M. Pedram, "FPGA Synthesis using OBDD-based Function Decomposition," USC Technical Flep ort, 1994.

Google Scholar

[11]

P. Molitor and C. Scholl, "Communication Based Multilevel Synthesis for Multi-Output Boolean Functions," 4th Great Lakes Symposium on VLSL Indiana, 1994.

Google Scholar

[12]

Y.-T. Lai, M. Pedram, and S. B. K. Vrudhula, "EVBDD-Based Algorithms for Integer Linear Programming, Spectral Transformation, and Function Decomposition," IEEE Transactions on Computer-Aided Design, vol. 13, no. 8, 1994.

Digital Library

Google Scholar

[13]

O. Coudert, J. C. Madre, and H. Fraisse, "A New Viewpoint on Two-Level Minimization," 30th A CM/IEEE Design Automation Conference, DAC, 1993.

Digital Library

Google Scholar

[14]

T. Kam, T. Villa, R. Brayton, and A. Sangiovanni-Vincentelli, "A Fully Implicit Algorithm for Exact State Minimization," 31th A CM/IEEE Design Automation Conference DA C, 1994.

Digital Library

Google Scholar

[15]

U. Schlichtmann, "Disjunkte Dekomposition Boolescher Funktionen: Eine Neue Betrachtungsweise," Tagungsband 6. E.LS.- Workshop, pp. 319- 328, Nov. 1993.

Google Scholar

[16]

E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Sequential Circuit Design Using Synthesis and Optimization," IEEE/A CM International Conference on Computer-Aided Design, ICCAD, pp. 328-333, Oct. 1992.

Digital Library

Google Scholar

Cited By

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Kubica MOpara AKania DKubica MOpara AKania D(2020)Partial Sharing of Logic ResourcesTechnology Mapping for LUT-Based FPGA10.1007/978-3-030-60488-2_9(93-113)Online publication date: 8-Nov-2020
https://doi.org/10.1007/978-3-030-60488-2_9
Schlichtmann UDavoodi AYoung E(2015)Beyond GORDIAN and KraftwerkProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2723571(133-140)Online publication date: 29-Mar-2015
https://dl.acm.org/doi/10.1145/2717764.2723571
Lin XDagless ELu A(2005)Technology mapping of LUT based FPGAs for delay optimisationField-Programmable Logic and Applications10.1007/3-540-63465-7_229(245-254)Online publication date: 29-Jul-2005
https://doi.org/10.1007/3-540-63465-7_229
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Index Terms

Functional multiple-output decomposition: theory and an implicit algorithm
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Integrated circuits
    1. Logic circuits

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DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

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Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1995

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Kubica MOpara AKania DKubica MOpara AKania D(2020)Partial Sharing of Logic ResourcesTechnology Mapping for LUT-Based FPGA10.1007/978-3-030-60488-2_9(93-113)Online publication date: 8-Nov-2020
https://doi.org/10.1007/978-3-030-60488-2_9
Schlichtmann UDavoodi AYoung E(2015)Beyond GORDIAN and KraftwerkProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2723571(133-140)Online publication date: 29-Mar-2015
https://dl.acm.org/doi/10.1145/2717764.2723571
Lin XDagless ELu A(2005)Technology mapping of LUT based FPGAs for delay optimisationField-Programmable Logic and Applications10.1007/3-540-63465-7_229(245-254)Online publication date: 29-Jul-2005
https://doi.org/10.1007/3-540-63465-7_229
Legl CEckl KWurth B(2005)Performance-directed technology mapping for LUT-based FPGAs — What role do decomposition and covering play?Field-Programmable Logic Smart Applications, New Paradigms and Compilers10.1007/3-540-61730-2_2(14-23)Online publication date: 6-Jun-2005
https://doi.org/10.1007/3-540-61730-2_2
Sasao TMatsuura MMalik SFix LKahng A(2004)A method to decompose multiple-output logic functionsProceedings of the 41st annual Design Automation Conference10.1145/996566.996689(428-433)Online publication date: 7-Jun-2004
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Kravets VSakallah KPileggi LKuehlmann A(2002)Resynthesis of multi-level circuits under tight constraints using symbolic optimizationProceedings of the 2002 IEEE/ACM international conference on Computer-aided design10.1145/774572.774673(687-693)Online publication date: 10-Nov-2002
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Kravets VSakallah K(2002)Resynthesis of multi-level circuits under tight constraints using symbolic optimizationIEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.10.1109/ICCAD.2002.1167606(687-693)Online publication date: 2002
https://doi.org/10.1109/ICCAD.2002.1167606
Drechsler R(2002)Verifying integrity of decision diagramsIntegration, the VLSI Journal10.1016/S0167-9260(02)00042-132:1-3(61-75)Online publication date: 1-Nov-2002
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Yan KGoto S(2001)Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocksProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370330(231-234)Online publication date: 30-Jan-2001
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Yan K(2001)Logic synthesis for CPLDs and FPGAs with PLA-style logic blocksVLSI Design 2001. Fourteenth International Conference on VLSI Design10.1109/ICVD.2001.902675(291-297)Online publication date: 2001
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Nakagami‐m approximations for multiple‐input multiple‐output singular value decomposition transmissions

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Nakagami‐m approximations for multiple‐input multiple‐output singular value decomposition transmissions

The Fading Number of Memoryless Multiple-Input Multiple-Output Fading Channels

Joint transmit and receive filters design for multiple-input multiple-output (MIMO) systems

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