The RISC processor DMN-6: a unified data-control flow architecture

This work presents an academic RISC processor architecture, named DMN-6 that executes every instruction in the datapath. It concentrates all the movement, branch and alu instructions in the arithmetic-logic unit. The idea is to normalize the control signal generation for an integer functional unit. This is obtained by implementing a number of queue registers of different deepness around the datapath unit. These queues will control an assigned logic corresponding to a stage in the pipeline. The architecture reduces even more the complexity of a pipelined program execution. The main features are : Load/Store architecture, 4-stage pipeline, integer arithmetic, sixteen byte registers, internal separate data and instruction main memories, thirteen 16-bit instruction words.