Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/2656045.2656063acmconferencesArticle/Chapter ViewAbstractPublication PagesesweekConference Proceedingsconference-collections
research-article

Parallel many-core avionics systems

Published: 12 October 2014 Publication History

Abstract

Integrated Modular Avionics (IMA) enables incremental qualification by encapsulating avionics applications into software partitions (SWPs), as defined by the ARINC 653 standard. SWPs, when running on top of single-core processors, provide robust time partitioning as a means to isolate SWPs timing behavior from each other. However, when moving towards parallel execution in many-core processors, the simultaneous accesses to shared hardware and software resources influence the timing behavior of SWPs, defying the purpose of time partitioning to provide isolation among applications. In this paper, we extend the concept of SWP by introducing parallel software partitions (pSWP) specification that describes the behavior of SWPs required when running in a many-core to enable incremental qualification. pSWP are supported by a new hardware feature called guaranteed resource partition (GRP) that defines an execution environment in which SWPs run and that controls interferences in the accesses to shared hardware resources among SWPs such that time composability can be guaranteed.

References

[1]
Kalray MPPA 256 Many-Core Processor, http://www.kalray.eu/products/mppa-manycore,.
[2]
NanoC: http://www.nanoc-project.eu.
[3]
Precision Timed (PRET) Machines. http://chess.eecs.berkeley.edu/pret.
[4]
ARINC Specification 653: Avionics Application Software Standard Standard Interface, Part 1 and 4, 2012.
[5]
Soclib, http://www.soclib.fr/trac/dev, 2012.
[6]
B. Akesson, et. al. Predator: a predictable sdram memory controller. In CODES+ISSS, 2007.
[7]
W. Dally and B. Towles. Principles and Practices of Interconnection Networks. Elsevier, May 2004.
[8]
R. Fuchsen. How to address certification for multi-core based IMA platforms: Current status and potential solutions. In DACS, 2010.
[9]
M. Gerdes, et. al. The split-phase synchronisation technique: Reducing the pessimism in the WCET analysis of parallelised hard real-time programs. In RTCSA, 2012.
[10]
M. Gerdes, et. al. Time analysable synchronisation techniques for parallelised hard real-time applications. In DATE, 2012.
[11]
K. Goossens, et. al. Virtual execution platforms for mixed-time-criticality systems: The compsoc architecture and design flow. SIGBED Rev., 10(3):23--34, October 2013.
[12]
B. Jacob, et. al. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann Publishers Inc., 2007.
[13]
J. Jalle, et. al. Deconstructing bus access control policies for real-time multicores. In SIES, 2013.
[14]
T. Kelter, et. al. Static analysis of multi-core tdma resource arbitration delays. Real-Time Systems, 2013.
[15]
H. Kopetz and G. Bauer. The time-triggered architecture. Proc. of the IEEE, 91(1):112--126, 2003.
[16]
Yan Li, et. al. Timing analysis of concurrent programs running on shared cache multi-cores. In RTSS, 2009.
[17]
MERASA. EU-FP7 Project: www.merasa.org.
[18]
Jan Nowotsch and Michael Paulitsch. Leveraging multi-core computing architectures in avionics. In EDCC, 2012.
[19]
H. Ozaktas, et. al. Automatic wcet analysis of real-time parallel applications. In WCET workshop, 2013.
[20]
M. Panic, et. al. Parallel many-core avionics systems. Technical Report UPC-DAC-RR-CAP-2014-6, UPC, 2014.
[21]
M. Paolieri, et. al. Hardware support for wcet analysis of hard real-time multicore systems. In ISCA, 2009.
[22]
M. Paolieri, et. al. Timing effects of the memory system in real-time multicore integrated architectures: Problems and solutions. In TECS, 2012.
[23]
P. Radojkovic, et. al. On the evaluation of the impact of shared resources in multithreaded cots processors in time-critical environments. In HiPEAC, 2012.
[24]
D. Rahmati, et. al. Computing accurate performance bounds for best effort networks-on-chip. IEEE Trans. on Computers, 62(3), 2013.
[25]
J. Rattner. Single-chip cloud computer: An experimental many-core processor from Intel Labs.
[26]
A. Roca, et. al. Enabling high-performance crossbars through a floorplan-aware design. In ICPP, 2012.
[27]
C. Rochange, et. al. WCET analysis of a parallel 3D multigrid solver executed on the MERASA multi-core. In WCET workshop, 2010.
[28]
S. Schliecker, et. al. Bounding the shared resource load for the performance analysis of multiprocessor systems. In DATE, 2010.
[29]
A. Schranzhofer, et. al. Timing analysis for TDMA arbitration in resource sharing systems. In RTAS, 2010.
[30]
A. Schranzhofer, et. al. Timing analysis for resource access interference on adaptive resource arbiters. In RTAS, 2011.
[31]
Zheng Shi, et. al. Schedulability analysis for real time on-chip communication with wormhole switching. In IJERTCS, volume 1, 2010.
[32]
J. Sparsoe. Design of networks-on-chip for real-time multi-processor systems-on-chip. In ACSD, 2012.
[33]
Y. Tamir and G. L. Frazier. High-performance multiqueue buffers for VLSI communication switches. In ISCA, 1988.
[34]
Tilera Corporation. Tile Processor, User Architecture Manual, release 2.4, DOC.NO. UG101, 2011.
[35]
R. Wilhelm, et. al. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. Trans. Comp.-Aided Des. Integ. Cir. Sys., 28(7), 2009.

Cited By

View all
  • (2019)Improving Reliability of Multi-/Many-Core Processors by Using NMR-MPar ApproachRadiation Effects on Integrated Circuits and Systems for Space Applications10.1007/978-3-030-04660-6_8(175-203)Online publication date: 11-Apr-2019
  • (2018)Evaluation by Neutron Radiation of the NMR-MPar Fault-Tolerance Approach Applied to Applications Running on a 28-nm Many-Core ProcessorElectronics10.3390/electronics71103127:11(312)Online publication date: 8-Nov-2018
  • (2018)NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core ProcessorsApplied Sciences10.3390/app80304658:3(465)Online publication date: 17-Mar-2018
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
EMSOFT '14: Proceedings of the 14th International Conference on Embedded Software
October 2014
301 pages
ISBN:9781450330527
DOI:10.1145/2656045
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 12 October 2014

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Research-article

Funding Sources

Conference

ESWEEK'14
ESWEEK'14: TENTH EMBEDDED SYSTEM WEEK
October 12 - 17, 2014
New Delhi, India

Acceptance Rates

Overall Acceptance Rate 60 of 203 submissions, 30%

Upcoming Conference

ESWEEK '24
Twentieth Embedded Systems Week
September 29 - October 4, 2024
Raleigh , NC , USA

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)4
  • Downloads (Last 6 weeks)0
Reflects downloads up to 21 Sep 2024

Other Metrics

Citations

Cited By

View all
  • (2019)Improving Reliability of Multi-/Many-Core Processors by Using NMR-MPar ApproachRadiation Effects on Integrated Circuits and Systems for Space Applications10.1007/978-3-030-04660-6_8(175-203)Online publication date: 11-Apr-2019
  • (2018)Evaluation by Neutron Radiation of the NMR-MPar Fault-Tolerance Approach Applied to Applications Running on a 28-nm Many-Core ProcessorElectronics10.3390/electronics71103127:11(312)Online publication date: 8-Nov-2018
  • (2018)NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core ProcessorsApplied Sciences10.3390/app80304658:3(465)Online publication date: 17-Mar-2018
  • (2018)EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285729837:11(2451-2461)Online publication date: Nov-2018
  • (2016)Improving performance guarantees in wormhole mesh NoC designsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972154(1485-1488)Online publication date: 14-Mar-2016
  • (2016)Parallelizing Industrial Hard Real-Time Applications for the parMERASA MulticoreACM Transactions on Embedded Computing Systems10.1145/291058915:3(1-27)Online publication date: 23-May-2016
  • (2015)Seeking Time-Composable Partitions of Tasks for COTS Multicore ProcessorsProceedings of the 2015 IEEE 18th International Symposium on Real-Time Distributed Computing10.1109/ISORC.2015.43(208-217)Online publication date: 13-Apr-2015

View Options

Get Access

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media