invited-talk

Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper

Authors:

Herman Schmit,

Randy HuangAuthors Info & Claims

ISLPED '16: Proceedings of the 2016 International Symposium on Low Power Electronics and Design

Pages 152 - 153

https://doi.org/10.1145/2934583.2953983

Published: 08 August 2016 Publication History

Get Access

Abstract

Intel's Xeon roadmap includes package-integrated FPGAs in every new generation. In this talk, we will dissect why this is such a powerful combination at this time of great change in datacenter workloads. We will show how power savings within the CPU complex is a significant multiplier for power savings in the datacenter as a whole. Focusing on the domain of machine learning, we will present the recent evolution of data types and operators, and make the case that FPGAs are the path to facilitate this continued evolution. Finally, we will discuss the criticality of the close coupling of the CPU and the FPGA. This coupling facilitates high bandwidth and low latency communication that is required for the development, debugging and deployment of heterogeneous applications.

References

[1]

National Resource Defense Council, "Data Center Efficiency Assessment", https://www.nrdc.org/sites/default/files/data-center-efficiency-assessment-IP.pdf Retrieved June 27, 2016.

Google Scholar

[2]

Emerson Network Power, "Energy Logic: Reducing Data Center Energy Consumption by Creating Savings that Cascade Across System," http://whitepapers.datacenterknowledge.com/content10394 Retreived June 27, 2016

Google Scholar

[3]

Krizhevsky, Alex. "ImageNet Classification with Deep Convolutional Neural Networks" http://www.image-net.org/challenges/LSVRC/2012/supervision.pdf, Retrieved 17 November 2013.

Google Scholar

[4]

Rastegari, Mohammad, Ordonez, Vicente, Redmon, Joseph, and Farhadi, Ali. Xnornet: Imagenet classification using binary convolutional neural networks. arXiv preprint arXiv:1603.05279, 2016.

Google Scholar

[5]

Li, Fengfu and Liu, Bin. Ternary weight networks. arXiv preprint arXiv:1605.04711, 2016.

Google Scholar

[6]

Zhou, Ni, Zhou, Wen, Wu, and Zou, DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients. arXiv preprint arXiv:1606.06160.

Google Scholar

[7]

Harris, M, Inside Pascal: NVIDIA's Newest Computing Platform, https://devblogs.nvidia.com/parallelforall/insidepascal, Retrieved on June 30, 2016.

Google Scholar

[8]

Tensor Processing Unit. retrieved from https://en.wikipedia.org/wiki/Tensor_processing_unit Retrieved on June 30, 2016.

Google Scholar

[9]

Compton, K., and Hauck, S.: 'Reconfigurable computing: a survey of systems and software', ACM Comput. Surv., 2002, 34, (2), pp. 171--210.

Digital Library

Google Scholar

Cited By

View all

Holzinger PReichenbach M(2021)The HERA Methodology: Reconfigurable Logic in General-Purpose ComputingIEEE Access10.1109/ACCESS.2021.31238749(147212-147236)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3123874
Cho HOh PPark JJung WLee JBahar IHerlihy MWitchel ELebeck A(2019)FA3CProceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304058(499-513)Online publication date: 4-Apr-2019
https://dl.acm.org/doi/10.1145/3297858.3304058
Cheng XLiu CHe B(2019)Emerging Hardware TechnologiesEncyclopedia of Big Data Technologies10.1007/978-3-319-77525-8_170(699-703)Online publication date: 20-Feb-2019
https://doi.org/10.1007/978-3-319-77525-8_170
Show More Cited By

Recommendations

Evaluation of Rodinia Codes on Intel Xeon Phi
ISMS '13: Proceedings of the 2013 4th International Conference on Intelligent Systems, Modelling and Simulation

High performance computing (HPC) is a niche area where various parallel benchmarks are constantly used to explore and evaluate the performance of Heterogeneous computing systems on the horizon. The Rodinia benchmark suite, a collection of parallel ...
Intel Xeon Phi Coprocessor Architecture and Tools: The Guide for Application Developers
Practical SIMD Vectorization Techniques for Intel® Xeon Phi Coprocessors
IPDPSW '13: Proceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum

Intel® Xeon Phi™ coprocessor is based on the Intel® Many Integrated Core (Intel® MIC) architecture, which is an innovative new processor architecture that combines abundant thread parallelism with long SIMD vector units. Efficiently exploiting SIMD ...

Comments

Information & Contributors

Information

Published In

ISLPED '16: Proceedings of the 2016 International Symposium on Low Power Electronics and Design

August 2016

392 pages

ISBN:9781450341851

DOI:10.1145/2934583

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 August 2016

Check for updates

Qualifiers

Invited-talk
Research
Refereed limited

Conference

ISLPED '16

Sponsor:

SIGDA

ISLPED '16: International Symposium on Low Power Electronics and Design

August 8 - 10, 2016

CA, San Francisco Airport, USA

Acceptance Rates

ISLPED '16 Paper Acceptance Rate 60 of 190 submissions, 32%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
272
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)0

Reflects downloads up to 22 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Holzinger PReichenbach M(2021)The HERA Methodology: Reconfigurable Logic in General-Purpose ComputingIEEE Access10.1109/ACCESS.2021.31238749(147212-147236)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3123874
Cho HOh PPark JJung WLee JBahar IHerlihy MWitchel ELebeck A(2019)FA3CProceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304058(499-513)Online publication date: 4-Apr-2019
https://dl.acm.org/doi/10.1145/3297858.3304058
Cheng XLiu CHe B(2019)Emerging Hardware TechnologiesEncyclopedia of Big Data Technologies10.1007/978-3-319-77525-8_170(699-703)Online publication date: 20-Feb-2019
https://doi.org/10.1007/978-3-319-77525-8_170
Cheng XLiu CHe B(2018)Emerging Hardware TechnologiesEncyclopedia of Big Data Technologies10.1007/978-3-319-63962-8_170-1(1-5)Online publication date: 20-Apr-2018
https://doi.org/10.1007/978-3-319-63962-8_170-1
Marques DDuarte HIlic ASousa LBelenov RThierry PMatveev Z(2017)Performance Analysis with Cache-Aware Roofline Model in Intel Advisor2017 International Conference on High Performance Computing & Simulation (HPCS)10.1109/HPCS.2017.150(898-907)Online publication date: Jul-2017
https://doi.org/10.1109/HPCS.2017.150

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Recommendations

Evaluation of Rodinia Codes on Intel Xeon Phi

Intel Xeon Phi Coprocessor Architecture and Tools: The Guide for Application Developers

Practical SIMD Vectorization Techniques for Intel® Xeon Phi Coprocessors

Comments

Published In

Sponsors

Publisher

Publication History

Check for updates

Qualifiers

Conference

Acceptance Rates

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

Abstract

References

Cited By

Recommendations

Evaluation of Rodinia Codes on Intel Xeon Phi

Intel Xeon Phi Coprocessor Architecture and Tools: The Guide for Application Developers

Practical SIMD Vectorization Techniques for Intel® Xeon Phi Coprocessors

Comments

Information

Published In

Sponsors

Publisher

Publication History

Check for updates

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Get Access

Login options

Full Access

View options

PDF

eReader

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations

Practical SIMD Vectorization Techniques for Intel® Xeon Phi Coprocessors