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Hierarchical placement directives for parametric IP blocks

Published: 01 February 1999 Publication History

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  • (1999)XCC-a tool for designing parameterizable IP cores in VHDLConference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020)10.1109/ACSSC.1999.832429(752-756)Online publication date: 1999

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cover image ACM Conferences
FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
February 1999
257 pages
ISBN:1581130880
DOI:10.1145/296399
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 01 February 1999

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FPGA99
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FPGA99: ACM/SIGDA Symposium on Field Programmable Gate Arrays
February 21 - 23, 1999
California, Monterey, USA

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  • (1999)XCC-a tool for designing parameterizable IP cores in VHDLConference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020)10.1109/ACSSC.1999.832429(752-756)Online publication date: 1999

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