research-article

GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures

Authors:

Ziad Abuowaimer,

Timothy Martin,

Jeremy Foxcroft,

Anthony VannelliAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 23, Issue 5

Article No.: 66, Pages 1 - 33

https://doi.org/10.1145/3233244

Published: 12 October 2018 Publication History

Abstract

Optimizing for routability during FPGA placement is becoming increasingly important, as failure to spread and resolve congestion hotspots throughout the chip, especially in the case of large designs, may result in placements that either cannot be routed or that require the router to work excessively hard to obtain success. In this article, we introduce a new, analytic routability-aware placement algorithm for Xilinx UltraScale FPGA architectures. The proposed algorithm, called GPlace3.0, seeks to optimize both wirelength and routability. Our work contains several unique features including a novel window-based procedure for satisfying legality constraints in lieu of packing, an accurate congestion estimation method based on modifications to the pathfinder global router, and a novel detailed placement algorithm that optimizes both wirelength and external pin count. Experimental results show that compared to the top three winners at the recent ISPD’16 FPGA placement contest, GPlace3.0 is able to achieve (on average) a 7.53%, 15.15%, and 33.50% reduction in routed wirelength, respectively, while requiring less overall runtime. As well, an additional 360 benchmarks were provided directly from Xilinx Inc. These benchmarks were used to compare GPlace3.0 to the most recently improved versions of the first- and second-place contest winners. Subsequent experimental results show that GPlace3.0 is able to outperform the improved placers in a variety of areas including number of best solutions found, fewest number of benchmarks that cannot be routed, runtime required to perform placement, and runtime required to perform routing.

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Cited By

Pennicard DRahmani VGraafsma H(2024)Data reduction and processing for photon science detectorsFrontiers in Physics10.3389/fphy.2024.128585412Online publication date: 5-Feb-2024
https://doi.org/10.3389/fphy.2024.1285854
Thurmer KBetz V(2024)VIPER: A VTR Interface for Placement with Error ResilienceProceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3665283.3665300(99-108)Online publication date: 19-Jun-2024
https://dl.acm.org/doi/10.1145/3665283.3665300
Di ZTao RMai JChen LLin Y(2024)LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line MinimizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.334055471:3(1259-1272)Online publication date: Mar-2024
https://doi.org/10.1109/TCSI.2023.3340554
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Index Terms

GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Integrated circuits
    1. Reconfigurable logic and FPGAs

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 23, Issue 5

September 2018

310 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3268934

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2018 ACM.

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 12 October 2018

Accepted: 01 June 2018

Revised: 01 April 2018

Received: 01 November 2017

Published in TODAES Volume 23, Issue 5

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Cited By

Pennicard DRahmani VGraafsma H(2024)Data reduction and processing for photon science detectorsFrontiers in Physics10.3389/fphy.2024.128585412Online publication date: 5-Feb-2024
https://doi.org/10.3389/fphy.2024.1285854
Thurmer KBetz V(2024)VIPER: A VTR Interface for Placement with Error ResilienceProceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3665283.3665300(99-108)Online publication date: 19-Jun-2024
https://dl.acm.org/doi/10.1145/3665283.3665300
Di ZTao RMai JChen LLin Y(2024)LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line MinimizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.334055471:3(1259-1272)Online publication date: Mar-2024
https://doi.org/10.1109/TCSI.2023.3340554
Mai JWang JDi ZLin Y(2024)Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331310143:2(641-653)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3313101
Mai JWang JChen YGuo ZJiang XLiang YLin Y(2024)OpenPARF 3.0: Robust Multi-Electrostatics Based FPGA Macro Placement Considering Cascaded Macros Groups and Fence Regions2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617535(374-379)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617535
Xiong ZRajarathnam RPan D(2024)A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM60383.2024.00022(115-125)Online publication date: 5-May-2024
https://doi.org/10.1109/FCCM60383.2024.00022
Rahmani VNawaz SPennicard DGraafsma H(2024)Robust image descriptor for machine learning based data reduction in serial crystallographyJournal of Applied Crystallography10.1107/S160057672400147X57:2(413-430)Online publication date: 26-Mar-2024
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Tu KTang XYu CJosipović LChu ZTu KTang XYu CJosipović LChu Z(2024)Physical ImplementationFPGA EDA10.1007/978-981-99-7755-0_10(165-206)Online publication date: 1-Feb-2024
https://doi.org/10.1007/978-981-99-7755-0_10
Yu LGuo B(2023)Timing-Driven Simulated Annealing for FPGA Placement in Neural Network RealizationElectronics10.3390/electronics1217356212:17(3562)Online publication date: 23-Aug-2023
https://doi.org/10.3390/electronics12173562
Rajarathnam RJiang ZIyer MPan DChinnery DHui-Ru Jiang I(2023)DREAMPlaceFPGA-PLProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3571881(175-184)Online publication date: 26-Mar-2023
https://dl.acm.org/doi/10.1145/3569052.3571881
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