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LiTM: A Lightweight Deterministic Software Transactional Memory System
Deterministic software transactional memory (STM) is a useful programming model for writing parallel codes, as it improves programmability (by supporting transactions) and debuggability (by supporting determinism). This paper presents LiTM, a new ...
Don't Forget About Synchronization!: A Case Study of K-Means on GPU
Heterogeneous devices are becoming necessary components of high performance computing infrastructures, and the graphics processing unit (GPU) plays an important role in this landscape. Given a problem, the established approach for exploiting the GPU is ...
Gecko: Hierarchical Distributed View of Heterogeneous Shared Memory Architectures
The November 2018 TOP500 report shows that 86 systems in the list are heterogeneous systems configured with accelerators and co-processors, of which 60 use NVIDIA GPUs, 21 use Intel Xeon Phi cards, one uses AMD FirePro GPUs, one uses PEZY technology, ...
Brie: A Specialized Trie for Concurrent Datalog
Modern Datalog engines are employed in industrial applications such as graph databases, networks, and static program analysis. To cope with the vast amount of data in these applications, Datalog engines must employ specialized parallel data structures. ...
Wait-free Dynamic Transactions for Linked Data Structures
Transactional data structures support threads executing a sequence of operations atomically. Dynamic transactions allow operands to be generated on the fly and allows threads to execute code in between the operations of a transaction, in contrast to ...
Deciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures
Heterogeneous architectures have become increasingly common. From co-packaging small and large cores, to GPUs alongside CPUs, to general-purpose heterogeneous-ISA architectures with cores implementing different ISAs. As diversity of execution cores ...
Formal Verification through Combinatorial Topology: the CAS-Extended Model
Wait-freedom guarantees that all processes complete their operations in a finite number of steps regardless of the delay of any process. Combinatorial topology has been proposed in the literature as a formal verification technique to prove the wait-free ...
Process Barrier for Predictable and Repeatable Concurrent Execution
We study on how to design, debug and verify and validate (V&V) safety-critical control software running on shared-memory many-core platforms. Managing concurrency in a verifiable way is a certification requirement. The presented process barrier is a ...
libMPNode: An OpenMP Runtime For Parallel Processing Across Incoherent Domains
In this work we describe libMPNode, an OpenMP runtime designed for efficient multithreaded execution across systems composed of multiple non-cache-coherent domains. Rather than requiring extensive compiler-level transformations or building new ...
Task-DAG Support in Single-Source PHAST Library: Enabling Flexible Assignment of Tasks to CPUs and GPUs in Heterogeneous Architectures
Nowadays, the majority of desktop, mobile, and embedded devices in the consumer and industrial markets are heterogeneous, as they contain at least multi-core CPU and GPU resources in the same system. However, exploiting the performance and energy-...
Index Terms
- Proceedings of the 10th International Workshop on Programming Models and Applications for Multicores and Manycores