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CYCLONE: automated design and layout of RF LC-oscillators

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W. SansenAuthors Info & Claims

DAC '00: Proceedings of the 37th Annual Design Automation Conference

Pages 11 - 14

https://doi.org/10.1145/337292.337301

Published: 01 June 2000 Publication History

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Abstract

This paper presents an automated, layout-aware RF LC-oscillator design tool, called CYCLONE that delivers an accurate and optimal LC-oscillator design, from specification to layout. The tool combines the accuracy of device-level simulation and finite element analysis with the optimisation power of simulated annealing algorithms and is verified with experimental results.

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Cited By

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Yin SWang RZhang JLiu XWang Y(2024)Automatic Design for W-Band Front-End System via Bottom-Up Sizing and Layout GenerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332904043:3(705-715)Online publication date: Mar-2024
https://doi.org/10.1109/TCAD.2023.3329040
Martins RLourenço N(2023)Analog Integrated Circuit Routing Techniques: An Extensive ReviewIEEE Access10.1109/ACCESS.2023.326548111(35965-35983)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3265481
Martins RLourenco NPovoa RCanelas AHorta NPassos FCastro-Lopez RRoca EFernandez F(2017)Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD.2017.7981577(1-4)Online publication date: Jun-2017
https://doi.org/10.1109/SMACD.2017.7981577
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Index Terms

CYCLONE: automated design and layout of RF LC-oscillators
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering
2. Hardware

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Published In

DAC '00: Proceedings of the 37th Annual Design Automation Conference

June 2000

819 pages

ISBN:1581131879

DOI:10.1145/337292

Chairman:
Giovanni De Micheli
Stanford Univ., Stanford, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 2000

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EDAC
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DAC00: ACM/IEEE-CAS/EDAC Design Automation Conference

June 5 - 9, 2000

California, Los Angeles, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Sponsor:
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June 22 - 26, 2025

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Cited By

View all

Yin SWang RZhang JLiu XWang Y(2024)Automatic Design for W-Band Front-End System via Bottom-Up Sizing and Layout GenerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332904043:3(705-715)Online publication date: Mar-2024
https://doi.org/10.1109/TCAD.2023.3329040
Martins RLourenço N(2023)Analog Integrated Circuit Routing Techniques: An Extensive ReviewIEEE Access10.1109/ACCESS.2023.326548111(35965-35983)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3265481
Martins RLourenco NPovoa RCanelas AHorta NPassos FCastro-Lopez RRoca EFernandez F(2017)Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD.2017.7981577(1-4)Online publication date: Jun-2017
https://doi.org/10.1109/SMACD.2017.7981577
Dündar GUnutulmaz A(2010)Routing Analog CircuitsAnalog Layout Synthesis10.1007/978-1-4419-6932-3_4(149-201)Online publication date: 25-Aug-2010
https://doi.org/10.1007/978-1-4419-6932-3_4
De Ranter CVan der Plas GSteyaert MGielen GSansen W(2006)CYCLONEIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2002.80226721:10(1161-1170)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2002.802267
Bhaduri AVijay VAgarwal AVemuri R(2004)Parasitic-aware synthesis of RF LNA circuits considering quasi-static extraction of inductors and interconnectsThe 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.10.1109/MWSCAS.2004.1354031(1_477-1_480)Online publication date: 2004
https://doi.org/10.1109/MWSCAS.2004.1354031
Vancorenland PCoppejans PDe Cock WLeroux PSteyaert MPileggi LKuehlmann A(2002)Optimization of a fully integrated low power CMOS GPS receiverProceedings of the 2002 IEEE/ACM international conference on Computer-aided design10.1145/774572.774618(305-308)Online publication date: 10-Nov-2002
https://dl.acm.org/doi/10.1145/774572.774618
De Ranter CSteyaert MDe VIrwin MVerbauwhede IPiguet C(2002)Design techniques for low power high bandwidth upconversion in CMOSProceedings of the 2002 international symposium on Low power electronics and design10.1145/566408.566469(237-242)Online publication date: 12-Aug-2002
https://dl.acm.org/doi/10.1145/566408.566469
Kratyuk VMayaram K(2002)VCOOPT: a tool for VCO phase noise optimizationProceedings RAWCON 2002. 2002 IEEE Radio and Wireless Conference (Cat. No.02EX573)10.1109/RAWCON.2002.1030147(181-184)Online publication date: 2002
https://doi.org/10.1109/RAWCON.2002.1030147
De Ranter CSteyaert M(2002)Design techniques for low power high bandwidth upconversion in CMOSProceedings of the International Symposium on Low Power Electronics and Design10.1109/LPE.2002.146745(237-242)Online publication date: 2002
https://doi.org/10.1109/LPE.2002.146745
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