- Sponsor:
- sigmicro
Powerful forces of innovation and demands from computing infrastructure are pushing the boundaries of traditional processing platforms in an unprecedented manner. Artificial Intelligence, Cybersecurity, Big Data, autonomous vehicles, 5G or NextG communication technologies, and Internet of Things (IoT) are some of the application areas where field of multi/many-core processing platforms are being used. This propels research towards novel architectures consisting of heterogeneous, accelerator-rich scenarios with highly specialized chiplets handling specialized task threads. Such massive integration both inside and across a single die imposes ever-increasing demand on the interconnection sub-system. Networks-on-Chips have been the de facto mechanism of connecting a scalable number of cores within the same die. However, the increasing power-performance demands as well the security requirements of the application domains require a constant churn of the interconnection architectures. The use of emerging technologies such as interposers, wireless and optical interconnects help alleviate some of these challenges while exposing other novel opportunities. This evolving landscape makes the interconnection architecture a critical determinant of power-performance bottlenecks as well as reliability and security of the overall system they are deployed in.
In this context, NoCArc continues its evolution and seeks to be a focused forum for researchers and practitioners to present and discuss innovative ideas and solutions related to the design, implementation, and application of interconnect fabrics within complex multi/many-core systems with conventional or emerging technologies such as 3D, optical, or wireless communications at the chip or system scale.
Proceeding Downloads
A scalable NoC topology targeting network performance
Scalability, path diversity, and bisection-width are the primary design concerns that significantly affect the NoC performance. The present work proposes an NoC topology taking into account the above design considerations. Rigorous experimentation is ...
Dead flit attack on NoC by hardware trojan and its impact analysis
With the advancement in VLSI technology, Tiled Chip Multicore Processors (TCMPs) with packet switched Network-on-Chip (NoC) have emerged as the most popular design choice for compute and data intensive embedded and parallel systems. Tight time-to-market ...
Performance analysis of application-specific instruction-set routers in networks-on-chip
Network-on-Chip (NoC) is a well-known communication infrastructure to design large scalable MPSoCs. Data transfers in NoCs can take up a significant part of a parallel application. To avoid that the communication costs decelerate the system performance, ...
Loopback strategy for in-vehicle network processing in automotive gateway network on chip
In this work, authors introduce an innovative loopback strategy for In-Vehicle Network (IVN) processing in automotive gateway (GW) Network on Chip. The new proposed architecture is fully HW centric, and allows performing any IVN processing algorithms ...
Machine learning for design and optimization challenges in multi/many-core network-on-chip
Due to the advancement of transistor technology, a single chip processor can now have hundreds of cores. Network-on-Chip (NoC) has been the superior interconnect fabric for multi/many-core on-chip systems because of its scalability and parallelism. Due ...
Index Terms
- Proceedings of the 14th International Workshop on Network on Chip Architectures
Recommendations
Acceptance Rates
Year | Submitted | Accepted | Rate |
---|---|---|---|
NoCArc '23 | 14 | 5 | 36% |
NoCArc '21 | 9 | 5 | 56% |
NoCArc '19 | 16 | 7 | 44% |
NoCArc '17 | 20 | 6 | 30% |
NoCArc '16 | 20 | 8 | 40% |
NoCArc '15 | 21 | 6 | 29% |
NoCArc '14 | 22 | 9 | 41% |
Overall | 122 | 46 | 38% |