Article

Circuit design of routing switches

Authors:

David LewisAuthors Info & Claims

FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays

Pages 19 - 28

https://doi.org/10.1145/503048.503052

Published: 24 February 2002 Publication History

Abstract

This paper examines circuit design of buffered routing switches in symmetrical, island-style FPGAs. The effects of switch size, tile length, level-restoring, and slow input slew rates are examined. Two new fanin-based switch designs are used to eliminate nearly all of the increase in delay that arises from fanout with a previous switch design. Alternating between buffers and pass transistors is shown to improve connection delay without fanout by 25%. To take advantage of this, we propose schemes to replace some buffers with pass transistors to simultaneously reduce area and delay. Routing a suite of MCNC benchmark circuits shows that 14% in area-delay, or 7% in delay can be saved using the new switch schemes. Alternatively, approximately 13% in area can be saved with no degradation to delay.

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Cited By

Rostami Sani SYe A(2024)Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nmACM Transactions on Reconfigurable Technology and Systems10.1145/363905517:1(1-29)Online publication date: 12-Feb-2024
https://dl.acm.org/doi/10.1145/3639055
Rostami-Sani SRazzaq AYe A(2022)Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM53951.2022.9786176(1-9)Online publication date: 15-May-2022
https://doi.org/10.1109/FCCM53951.2022.9786176
Saidi HTurki MMarrakchi ZAbid MObeid A(2022)Development and Analysis of Novel Mesh of Tree-based embedded FPGAThe Journal of Supercomputing10.1007/s11227-022-04569-278:16(17689-17720)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1007/s11227-022-04569-2
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Circuit design of routing switches
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Published In

cover image ACM Conferences

FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays

February 2002

257 pages

ISBN:1581134525

DOI:10.1145/503048

General Chair:
Martine Schlag,
Program Chair:
Steve Trimberger

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 February 2002

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FPGA02

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SIGDA

FPGA02: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 24 - 26, 2002

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Citations

Cited By

Rostami Sani SYe A(2024)Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nmACM Transactions on Reconfigurable Technology and Systems10.1145/363905517:1(1-29)Online publication date: 12-Feb-2024
https://dl.acm.org/doi/10.1145/3639055
Rostami-Sani SRazzaq AYe A(2022)Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM53951.2022.9786176(1-9)Online publication date: 15-May-2022
https://doi.org/10.1109/FCCM53951.2022.9786176
Saidi HTurki MMarrakchi ZAbid MObeid A(2022)Development and Analysis of Novel Mesh of Tree-based embedded FPGAThe Journal of Supercomputing10.1007/s11227-022-04569-278:16(17689-17720)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1007/s11227-022-04569-2
Chen XNi KNiemier MHan YDatta SHu X(2018)Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2018.2874880(1-14)Online publication date: 2018
https://doi.org/10.1109/TCSI.2018.2874880
Bai YLin M(2016)Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device TechnologyJournal of Low Power Electronics and Applications10.3390/jlpea60300156:3(15)Online publication date: 12-Aug-2016
https://doi.org/10.3390/jlpea6030015
Lewis DChiu GChromczak JGalloway DGamsa BManohararajah VMilton IVanderhoek TVan Dyken JChen DGreene J(2016)The Stratix™ 10 Highly Pipelined FPGA ArchitectureProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847267(159-168)Online publication date: 21-Feb-2016
https://dl.acm.org/doi/10.1145/2847263.2847267
ZamanZadeh SShahabi SJahanian A(2016)Security improvement of FPGA configuration file against the reverse engineering attack2016 13th International Iranian Society of Cryptology Conference on Information Security and Cryptology (ISCISC)10.1109/ISCISC.2016.7736459(101-105)Online publication date: Sep-2016
https://doi.org/10.1109/ISCISC.2016.7736459
Cuppini MMucci CFranchi Scarselli E(2015)Soft-Core Embedded-FPGA Based on Multistage Switching Networks: A Quantitative AnalysisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.238474023:12(3043-3052)Online publication date: Dec-2015
https://doi.org/10.1109/TVLSI.2014.2384740
Cong JXiao B(2014)FPGA-RPIIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.225951222:4(864-877)Online publication date: 1-Apr-2014
https://dl.acm.org/doi/10.1109/TVLSI.2013.2259512
Cuppini MScarselli EMucci C(2013)Design-space exploration of an eFPGA soft-core based on Multi-Stages Switching NetworksProceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)10.1109/PRIME.2013.6603104(133-136)Online publication date: Jun-2013
https://doi.org/10.1109/PRIME.2013.6603104
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