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An architecture of a dataflow single chip processor

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T. YubaAuthors Info & Claims

ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture

Pages 46 - 53

https://doi.org/10.1145/74925.74931

Published: 01 April 1989 Publication History

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Abstract

A highly parallel (more than a thousand) dataflow machine EM-4 is now under development. The EM-4 design principle is to construct a high performance computer using a compact architecture by overcoming several defects of dataflow machines. Constructing the EM-4, it is essential to fabricate a processing element (PE) on a single chip for reducing operation speed, system size, design complexity and cost. In the EM-4, the PE, called EMC-R, has been specially designed using a 50,000-gate gate array chip. This paper focuses on an architecture of the EMC-R. The distinctive features of it are: a strongly connected arc dataflow model; a direct matching scheme; a RISC-based design; a deadlock-free on-chip packet switch; and an integration of a packet-based circular pipeline and a register-based advanced control pipeline. These features are intensively examined, and the instruction set architecture and the configuration architecture which exploit them are described.

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An architecture of a dataflow single chip processor
1. Computer systems organization
  1. Architectures

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Published In

ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture

April 1989

426 pages

ISBN:0897913191

DOI:10.1145/74925

Chairman:
Jean-Claude Syre

ACM SIGARCH Computer Architecture News Volume 17, Issue 3
Special Issue: Proceedings of the 16th annual international symposium on Computer Architecture
June 1989
400 pages
ISSN:0163-5964
DOI:10.1145/74926
Editor:
Jean-Claude Syre
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Association for Computing Machinery

New York, NY, United States

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Published: 01 April 1989

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https://dl.acm.org/doi/10.1145/3381881
Toorn OSperotto A(2020)Looking Beyond the HorizonDigital Threats: Research and Practice10.1145/33736391:1(1-13)Online publication date: 17-Mar-2020
https://dl.acm.org/doi/10.1145/3373639
Bhargava VSaraf SVolkovich I(2020)Deterministic Factorization of Sparse Polynomials with Bounded Individual DegreeJournal of the ACM10.1145/336566767:2(1-28)Online publication date: 4-May-2020
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