Article

Power-aware clock tree planning

Authors:

Luca MazzoniAuthors Info & Claims

ISPD '04: Proceedings of the 2004 international symposium on Physical design

Pages 138 - 147

https://doi.org/10.1145/981066.981097

Published: 18 April 2004 Publication History

Abstract

Modern processors and SoCs require the adoption of power-oriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability of integrated circuits featuring nanometric technologies. And the power problem is further exacerbated by the increasing demand of devices for mobile, battery-operated systems, for which reduced power dissipation is mandatory. A large fraction of the power consumed by a synchronous circuit is due to the clock distribution network. This is for two reasons: First, the clock nets are long and heavily loaded. Second, they are subject to a high switching activity.The problem of automatically synthesizing a power efficient clock tree has been addressed recently in a few research contributions. In this paper, we introduce a methodology in which low-power clock trees are obtained through aggressive exploitation of the clock-gating technology. Distinguishing features of the methodology are: (i) The capability of calculating powerful clock-gating conditions that go beyond the simple topological search of the RTL source code. (ii) The capability of determining the clock tree logical structure starting from an RTL description. (iii) The capability of including in the cost function that drives the generation of the clock tree structure both functional (i.e., clock activation conditions) and physical (i.e., floorplanning) information. (iv) The capability of generating a clock tree structure that can be synthesized and routed using standard, commercially-available back-end tools.We illustrate the methodology for power-aware RTL clock tree planning, we provide details on the fundamental algorithms that support it and information on how such a methodology can be integrated into an industrial design flow. The results achieved on several benchmarks, as well as on a real design case demonstrate the feasibility and the potential of the proposed approach.

References

[1]

T. Mudge, "Power: A First-Class Architectural Design Constraint," IEEE Computer, Vol. 34, No. 4, pp. 52--58, April 2001.

Digital Library

[2]

V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, F. Baez, "Reducing Power in High-Performance Microprocessors," DAC-35: ACM/IEEE Design Automation Conference, pp. 732--737, San Francisco, CA, June 1998.

Digital Library

[3]

P. Gronowski, W. J. Bowhill, R. P. Preston, M. K. Gowan, R. L. Allmon, "High-Performance Microprocessor Design," IEEE Journal of Solid-State Circuits, Vol. 33, No. 5, pp. 676--686, May 1998.

[4]

D. R. Gonzales, "Micro-RISC Architecture for the Wireless Market," IEEE Micro, Vol. 19, No. 4, pp. 30--37, July-August 1999.

Digital Library

[5]

D. Duarte, V. Narayanan, M. J. Irwin, "Impact of Technology Scaling in the Clock System Power," IEEE Computer Society Annual Symposium on VLSI, pp. 52--57, Pittsburgh, PA, April 2002.

Digital Library

[6]

D. Duarte, V. Narayanan, M. J. Irwin, "A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations," IEEE Transactions on VLSI Systems, Vol. 10, No. 6, pp. 844--855, December 2002.

Digital Library

[7]

M. Donno, A. Ivaldi, L. Benini, E. Macii, "Clock-Tree Power Optimization based on RTL Clock-Gating," DAC-40: ACM/IEEE Design Automation Conference, pp. 622--627, Anaheim, CA, June 2003.

Digital Library

[8]

P. Babighian, L. Benini, E. Macii, "A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks," DATE-04: IEEE 2004 Design Automation and Test in Europe, pp. 500--505, Paris, France, February 2004.

Digital Library

[9]

J. G. Xi, W. W.-M. Dai, "Buffer Insertion and Sizing under Process Variations for Low-Power Clock Distribution," DAC-32: ACM/IEEE Design Automation Conference, pp. 491--496, San Francisco, CA, June 1995.

Digital Library

[10]

V. Adler, E. G. Friedman, "Repeater Insertion to Reduce Delay and Power in RC Tree Structures," IEEE Asilomar Conference on Signals, Systems and Computers, pp. 749--752, Pacific Grove, CA, November 1997.

[11]

J. Cong, C.-K. Koh; K.-S. Leung, "Simultaneous Buffer and Wire Sizing for Performance and Power Optimization," ISLPED-96: ACM/IEEE International Symposium on Low-Power Electronics and Design, pp. 271--276, Monterey, CA, August 1996.

Digital Library

[12]

A. Vittal, M. Marek-Sadowska, "Low-Power Buffered Clock Tree Design," IEEE Transactions on CAD/ICAS, Vol. 16, No. 9, pp. 965--975, September 1997.

Digital Library

[13]

M. Igarashi, K. Usami, K. Nogami, F. Minami, Y. Kawasaki, T. Aoki, M. Takano, C. Misuno, T. Ishikawa, M. Kanazawa, S. Sonoda, M. Ichida, N. Hatanaka, "A Low-Power Design Method using Multiple Supply Voltages," ISLPED-97: ACM/IEEE International Symposium on Low-Power Electronics and Design, pp. 36--41, Monterey, CA, August 1997.

Digital Library

[14]

J. Pangjun, S. S. Sapatnekar, "Clock Distribution using Multiple Voltages," ISLPED-99: ACM/IEEE International Symposium on Low-Power Electronics and Design, pp. 145--150, San Diego, CA, August 1999.

Digital Library

[15]

K. D. Boese, A. B. Kahng, "Zero-Skew Clock Routing Trees with Minimum Wire Length," IEEE International Conference on ASIC, pp. 1.1.1--1.1.5, Rochester, NY, September 1992.

[16]

T. H. Chao, Y. C. Hsu, J. M. Ho, "Zero Skew Clock Net Routing," DAC-29: ACM/IEEE Design Automation Conference, pp. 518--523, Anaheim, CA, June 1992.

Digital Library

[17]

M. Edahiro, "A Clustering-Based Optimization Algorithm in Zero-Skew Routing," DAC-30: ACM/IEEE Design Automation Conference, pp. 612--616, Dallas, TX, June 1993.

Digital Library

[18]

H. Zhang, J. Rabaey, "Low-Swing Interconnect Interface Circuits," ISLPED-98: ACM/IEEE International Symposium on Low-Power Electronics and Design, pp. 161--166, Monterey, CA, August 1998.

Digital Library

[19]

A. P. Chandrakasan, S. Sheng, R. W. Brodersen, "Low-Power CMOS Digital Design," IEEE Journal of Solid-State Circuits, Vol. 27, No. 4, pp. 473--484, April 1992.

[20]

L. Benini, P. Siegel, G. De Micheli, "Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits," IEEE Design and Test of Computers, Vol. 11, No. 4, pp. 32--40, December 1994.

Digital Library

[21]

L. Benini, G. De~Micheli, "Transformation and Synthesis of FSMs for Low-Power Gated-Clock Implementation," IEEE Transactions on CAD/ICAS, Vol. 15, No. 6, pp. 630--643, June 1996.

Digital Library

[22]

F. Theeuwen, E. Seelen, "Power Reduction Through Clock Gating by Symbolic Manipulation," VLSI: Integrated Systems on Silicon, pp. 389--400, Gramado, Rio Grande do Sul, Brazil, August 1997.

[23]

L. Benini, G. De Micheli, E. Macii, M. Poncino, R. Scarsi, "Symbolic Synthesis of Clock-Gating Logic for Power Optimization of Synchronous Controllers," ACM Transactions on Design Automation of Electronic Systems, Vol. 4, No. 4, pp. 351--375, October 1999.

Digital Library

[24]

L. Benini, M. Favalli, G. De Micheli, "Design for Testability of Gated-Clock FSMs," EDTC-96: IEEE European Design and Test Conference, pp. 589--596, Paris, France, March 1996.

Digital Library

[25]

D. Garrett, M. Stan, A. Dean, "Challenges in Clock Gating for a Low Power ASIC Methodology," ISLPED-99: ACM/IEEE International Symposium on Low-Power Electronics and Design, pp. 176--181, San Diego, CA, August 1999.

Digital Library

[26]

J. Oh, M. Pedram, "Gated Clock Routing for Low-Power Microprocessor Design," IEEE Transactions on CAD/ICAS, Vol. 20, No. 6, pp. 715--722, June 2001.

Digital Library

[27]

A. Farrahi, C. Chen, A. Srivastava, G. Tellez, M. Sarrafzadeh, "Activity-Driven Clock Design," IEEE Transactions on CAD/ICAS, Vol. 20, No. 6, pp. 705--714, June 2001.

Digital Library

[28]

T.-H. Chao, Y.-C. Hsu, J.-M. Ho, A. B. Khang, "Zero Skew Clock Routing with Minimum Wirelength," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 39, No. 11, pp. 799--814, November 1992.

[29]

C. Chen, C. Kang, M. Sarrafzadeh, "Activity-Sensitive Clock Tree Construction for Low Power," ISLPED-02: ACM/IEEE International Symposium on Low-Power Electronics and Design, pp. 279--282, Monterey, CA, August 2002.

Digital Library

[30]

M. Munch, B. Wurth, R. Mehra, J. Sproch, N. Wehn, "Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths," DATE-00: IEEE Design Automation and Test in Europe, pp. 624--631, Paris, France, March 2000.

Digital Library

Cited By

Khilko DStepchenkov YOrlov GGrigoriev ADiachenko Y(2024)Desynchronization of a Synchronous Circuit to Synthesize Self-Timed Circuit2024 Conference of Young Researchers in Electrical and Electronic Engineering (ElCon)10.1109/ElCon61730.2024.10468212(45-49)Online publication date: 29-Jan-2024
https://doi.org/10.1109/ElCon61730.2024.10468212
C JKumar KS CSreekanth TRao T(2023)Implementation of Routing-denser PnR Flow for an Efficient IC Block Level Design2023 Second International Conference on Trends in Electrical, Electronics, and Computer Engineering (TEECCON)10.1109/TEECCON59234.2023.10335847(293-297)Online publication date: 23-Aug-2023
https://doi.org/10.1109/TEECCON59234.2023.10335847
Takou AAxelou OFloros GEvmorfopoulos NStamoulis G(2023)An Optimal Methodology for EM-Based Hardware Trojan Placement on Clock Tree Networks2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS57524.2023.10405928(25-29)Online publication date: 6-Aug-2023
https://doi.org/10.1109/MWSCAS57524.2023.10405928
Show More Cited By

Index Terms

Power-aware clock tree planning
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Integrated circuits
    1. Logic circuits

Recommendations

Low-Power Clock Tree Synthesis for 3D-ICs

We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees’ dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock ...
Clock-tree power optimization based on RTL clock-gating
DAC '03: Proceedings of the 40th annual Design Automation Conference

As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing clock power based on clock gating. We present a methodology that, starting ...
Low-power clock distribution using multiple voltages and reduced swings

Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low-power clock tree by distributing the clock signal at a lower voltage and ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISPD '04: Proceedings of the 2004 international symposium on Physical design

April 2004

226 pages

ISBN:1581138172

DOI:10.1145/981066

General Chair:
Charles J. Alpert,
IBM
,
Program Chair:
Patrick Groeneveld
Eindhoven University

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 April 2004

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

ISPD04

Sponsor:

ISPD04: International Symposium on Physical Design 2004

April 18 - 21, 2004

Arizona, Phoenix, USA

Acceptance Rates

Overall Acceptance Rate 62 of 172 submissions, 36%

Upcoming Conference

ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

61
Total Citations
View Citations
1,339
Total Downloads

Downloads (Last 12 months)29
Downloads (Last 6 weeks)3

Reflects downloads up to 22 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Khilko DStepchenkov YOrlov GGrigoriev ADiachenko Y(2024)Desynchronization of a Synchronous Circuit to Synthesize Self-Timed Circuit2024 Conference of Young Researchers in Electrical and Electronic Engineering (ElCon)10.1109/ElCon61730.2024.10468212(45-49)Online publication date: 29-Jan-2024
https://doi.org/10.1109/ElCon61730.2024.10468212
C JKumar KS CSreekanth TRao T(2023)Implementation of Routing-denser PnR Flow for an Efficient IC Block Level Design2023 Second International Conference on Trends in Electrical, Electronics, and Computer Engineering (TEECCON)10.1109/TEECCON59234.2023.10335847(293-297)Online publication date: 23-Aug-2023
https://doi.org/10.1109/TEECCON59234.2023.10335847
Takou AAxelou OFloros GEvmorfopoulos NStamoulis G(2023)An Optimal Methodology for EM-Based Hardware Trojan Placement on Clock Tree Networks2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS57524.2023.10405928(25-29)Online publication date: 6-Aug-2023
https://doi.org/10.1109/MWSCAS57524.2023.10405928
Ding JLu LFu ZMa JGong MQi YYu W(2023)Clock Aware Low Power Placement2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323626(01-08)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323626
Beheshti-Shirazi SNazari NGubbi KLatibari BRafatirad SHomayoun HSasan AManoj P(2023)Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop MinimizationIEEE Access10.1109/ACCESS.2023.330453411(87869-87886)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3304534
Fatemi HKahng AKim Mde Gyvez JKahng A(2020)Optimal bounded-skew steiner trees to minimize maximum k-active dynamic powerProceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop10.1145/3414622.3431908(1-8)Online publication date: 5-Nov-2020
https://dl.acm.org/doi/10.1145/3414622.3431908
Seitanidis IDimitrakopoulos GMattheakis PMasse-Navette LChinnery D(2019)Timing-Driven and Placement-Aware Multibit Register CompositionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285274038:8(1501-1514)Online publication date: Aug-2019
https://doi.org/10.1109/TCAD.2018.2852740
Kim SLee SPark SKang S(2019)Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)10.1109/ISMVL.2019.00015(37-42)Online publication date: May-2019
https://doi.org/10.1109/ISMVL.2019.00015
Song XZhang SZhou JWang X(2019)A Variation Aware Register Clustering Methodology in Near-Threshold Region2019 IEEE 13th International Conference on ASIC (ASICON)10.1109/ASICON47005.2019.8983494(1-4)Online publication date: Oct-2019
https://doi.org/10.1109/ASICON47005.2019.8983494
Liu MZhang ZSun WWang D(2017)A novel obstacle-aware multiple fan-out symmetrical clock tree synthesisIEICE Electronics Express10.1587/elex.14.2017093514:20(20170935-20170935)Online publication date: 2017
https://doi.org/10.1587/elex.14.20170935
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents