Article

Design tradeoffs for tiled CMP on-chip networks

Authors:

William J. DallyAuthors Info & Claims

ICS '06: Proceedings of the 20th annual international conference on Supercomputing

Pages 187 - 198

https://doi.org/10.1145/1183401.1183430

Published: 28 June 2006 Publication History

Abstract

We develop detailed area and energy models for on-chip interconnection networks and describe tradeoffs in the design of efficient networks for tiled chip multiprocessors. Using these detailed models we investigate how aspects of the network architecture including topology, channel width, routing strategy, and buffer size affect performance and impact area and energy efficiency. We simulate the performance of a variety of on-chip networks designed for tiled chip multiprocessors implemented in an advanced VLSI process and compare area and energy efficiencies estimated from our models. We demonstrate that the introduction of a second parallel network can increase performance while improving efficiency, and evaluate different strategies for distributing traffic over the subnetworks. Drawing on insights from our analysis, we present a concentrated mesh topology with replicated subnetworks and express channels which provides a 24% improvement in area efficiency and a 48% improvement in energy efficiency over other networks evaluated in this study.

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Cited By

Kunthara RJames RSleeba SJose J(2024)Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-ChipJournal of Circuits, Systems and Computers10.1142/S021812662450207433:12Online publication date: 16-Feb-2024
https://doi.org/10.1142/S0218126624502074
Li SZhou SXue YFan WCheng TJi JDai CSong WChen QGao CLi LFu Y(2024)HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN AcceleratorsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.335991271:4(1863-1875)Online publication date: Apr-2024
https://doi.org/10.1109/TCSI.2024.3359912
Strikos PEjaz ASourdis I(2024)BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00025(167-178)Online publication date: 5-May-2024
https://doi.org/10.1109/ISPASS61541.2024.00025
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Design tradeoffs for tiled CMP on-chip networks

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We develop detailed area and energy models for on-chip interconnection networks and describe tradeoffs in the design of efficient networks for tiled chip multiprocessors. Using these detailed models we investigate how aspects of the network architecture ...
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Published In

cover image ACM Conferences

ICS '06: Proceedings of the 20th annual international conference on Supercomputing

June 2006

385 pages

ISBN:1595932828

DOI:10.1145/1183401

General Chairs:
Greg Egan
Monash University
,
Yoichi Muraoka
Waseda University

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 28 June 2006

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ICS06

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ICS06: International Conference on Supercomputing 2006

June 28 - July 1, 2006

Queensland, Cairns, Australia

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ICS '06 Paper Acceptance Rate 37 of 141 submissions, 26%;

Overall Acceptance Rate 629 of 2,180 submissions, 29%

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Cited By

Kunthara RJames RSleeba SJose J(2024)Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-ChipJournal of Circuits, Systems and Computers10.1142/S021812662450207433:12Online publication date: 16-Feb-2024
https://doi.org/10.1142/S0218126624502074
Li SZhou SXue YFan WCheng TJi JDai CSong WChen QGao CLi LFu Y(2024)HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN AcceleratorsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.335991271:4(1863-1875)Online publication date: Apr-2024
https://doi.org/10.1109/TCSI.2024.3359912
Strikos PEjaz ASourdis I(2024)BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00025(167-178)Online publication date: 5-May-2024
https://doi.org/10.1109/ISPASS61541.2024.00025
Roy AKapila VGupta APal R(2023)A Novel Network On Chip Architecture For FPGA Smart NIC2023 IEEE Women in Technology Conference (WINTECHCON)10.1109/WINTECHCON58518.2023.10276404(1-5)Online publication date: 21-Sep-2023
https://doi.org/10.1109/WINTECHCON58518.2023.10276404
Jain VCavalcante MBruschi NRogenmoser MBenz TKurth ARossi DBenini LVerhelst M(2023)PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247800(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247800
Yadav SLaxmi VKapoor HGaur MKumar A(2023)Adaptive distribution of control messages for improving bandwidth utilization in multiple NoCThe Journal of Supercomputing10.1007/s11227-023-05208-079:15(17208-17246)Online publication date: 7-May-2023
https://doi.org/10.1007/s11227-023-05208-0
Jain VVerhelst MJain VVerhelst M(2023)Networks-on-Chip to Enable Large-Scale Multi-core ML AccelerationTowards Heterogeneous Multi-core Systems-on-Chip for Edge Machine Learning10.1007/978-3-031-38230-7_8(143-161)Online publication date: 3-Jul-2023
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Pham-Quoc C(2023)A Survey of On-Chip Hybrid Interconnect for Multicore ArchitecturesContext-Aware Systems and Applications10.1007/978-3-031-28816-6_5(59-75)Online publication date: 24-Mar-2023
https://doi.org/10.1007/978-3-031-28816-6_5
Ejaz ASourdis I(2022)FastTrackNoC: A NoC with FastTrack Router Datapaths2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00075(971-985)Online publication date: Apr-2022
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Singh RBohra MHemrajani PKalla ABhatt DPurohit NDaneshtalab M(2022)Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCsIEEE Access10.1109/ACCESS.2022.322746010(129245-129268)Online publication date: 2022
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