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A linear-time heuristic for improving network partitions

Authors:

C. M. Fiduccia,

R. M. MattheysesAuthors Info & Claims

25 years of DAC: Papers on Twenty-five years of electronic design automation

Pages 241 - 247

https://doi.org/10.1145/62882.62910

Published: 01 June 1988 Publication History

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References

[1]

M A Breuer, "Min-Cut Placement, J. of Design and Fault- Tolerant Computing, Vol. I, number 4, Oct. 1977, pp. 343-362.

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M.A. Breuer, "A Class of Min-Cut Placement Algorithms, Proc. 14th Design Automation Conference, New Orleans, 1977, pp. 284-290.

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B.W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," Bell System Technical Journal, Vol. 49, Feb. 1970, pp. 291-307.

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D.G. Schweikert and B.W. Kernighan, "A Proper Model for the Partitioning of Electrical Circuits, Proc. 9th Design Automation Workshop, Dallas, June 1979, pp. 57-62.

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H. Shiraishi and F. Hirose, "Efficient Placement and Routing for Masterslice LSI, Proc. 17th Design Automation Conference, Minneapolis, June 1980, pp. 458-464.

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Cited By

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Li BYou HBi SZhang Y(2024)An Efficient Hypergraph Partitioner under Inter - Block Interconnection Constraints2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546878(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546878
Kim SPark H(2024)Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.335760043:7(1944-1956)Online publication date: Jul-2024
https://doi.org/10.1109/TCAD.2024.3357600
Bethur NAgnesina ABrunion MGarcia-Ortiz ACatthoor FMilojevic DKomalan MCavalcante MRiedel SBenini LLim S(2024)Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334275343:7(1957-1970)Online publication date: Jul-2024
https://doi.org/10.1109/TCAD.2023.3342753
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Index Terms

A linear-time heuristic for improving network partitions
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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25 years of DAC: Papers on Twenty-five years of electronic design automation

June 1988

630 pages

ISBN:0897912675

DOI:10.1145/62882

Editor:
A. R. Newton

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 01 June 1988

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Li BYou HBi SZhang Y(2024)An Efficient Hypergraph Partitioner under Inter - Block Interconnection Constraints2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546878(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546878
Kim SPark H(2024)Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.335760043:7(1944-1956)Online publication date: Jul-2024
https://doi.org/10.1109/TCAD.2024.3357600
Bethur NAgnesina ABrunion MGarcia-Ortiz ACatthoor FMilojevic DKomalan MCavalcante MRiedel SBenini LLim S(2024)Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334275343:7(1957-1970)Online publication date: Jul-2024
https://doi.org/10.1109/TCAD.2023.3342753
Xiao ZChen WQin YWu FChronopoulos ANicolau ALi K(2024)NGLIC: A Nonaligned-Row Legalization Approach for 3-D Interdie ConnectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331779443:2(404-416)Online publication date: Feb-2024
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Tang JBi SWu HYou H(2024)TBPart: An Effective Topological Order Balanced Hypergraph Partitioning Algorithm for VLSI Processor-based Hardware Emulation2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10618032(300-305)Online publication date: 10-May-2024
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Liu ZXie SZhang HZhou DYang Y(2024)A parallel computing framework for large-scale microscopic traffic simulation based on spectral partitioningTransportation Research Part E: Logistics and Transportation Review10.1016/j.tre.2023.103368181(103368)Online publication date: Jan-2024
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Ezilarasan MPreethi DLeung MChe HDai X(2024)Optimized VLSI Circuit Partitioning and Testing Using ACO and BIST ArchitecturesAdvances in Neural Networks – ISNN 202410.1007/978-981-97-4399-5_35(372-381)Online publication date: 7-Jul-2024
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Yu TGao PWang FYuan R(2024)Non‐overlapping placement of macro cells based on reinforcement learning in chip designInternational Journal of Circuit Theory and Applications10.1002/cta.4235Online publication date: 12-Aug-2024
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Arvanitakis IKranas GDossis MKakarountas ADadaliaris A(2023)Assessing Swapping Policies as a Detailed Placement Approach2023 8th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)10.1109/SEEDA-CECNSM61561.2023.10470672(1-6)Online publication date: 10-Nov-2023
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Lei ZXiao ZQin YLi K(2023)A Multi-Dimensional Weight Partition Algorithm for FPGA Prototype Simulation2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218647(106-109)Online publication date: 8-May-2023
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