Article

High level formal verification of next-generation microprocessors

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Tom SchubertAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 1 - 6

https://doi.org/10.1145/775832.775834

Published: 02 June 2003 Publication History

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Abstract

Formal property verification has been an effective complement to pre-silicon validation of several Intel Pentium 4 CPU designs at Intel Corporation. The principal objective of this program has been to prove design correctness rather than hunt for bugs. In the process, we have evolved our tools and methodology and are now applying FPV techniques to protocol level properties. Moving forward, new technologies such as GSTE and SAT offer the potential to significantly increase the scope of what can be formally verified. This paper will discuss the application of FPV to validation of the Intel Pentium 4 microarchitecture and some approaches being considered to broaden the application of FV techniques, particularly at a higher level of design abstraction.

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Cited By

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Cerny EDudani SHavlicek JKorchemny DCerny EDudani SHavlicek JKorchemny D(2014)Introduction to Assertion-Based Formal VerificationSVA: The Power of Assertions in SystemVerilog10.1007/978-3-319-07139-8_20(453-466)Online publication date: 8-Jul-2014
https://doi.org/10.1007/978-3-319-07139-8_20
Mitra SBanerjee ADasgupta PKumar H(2013)Counterexample Ranking Using Mined InvariantsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.227662732:12(1978-1991)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1109/TCAD.2013.2276627
Mitra SBanerjee ADasgupta PRosenstiel WMacii E(2012)Formal methods for ranking counterexamples through assumption miningProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492937(911-916)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492937
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Index Terms

High level formal verification of next-generation microprocessors
1. Hardware
  1. Hardware validation
    1. Functional verification

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Published In

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 02 June 2003

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formal property verification

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SIGDA

DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

CA, Anaheim, USA

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DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cerny EDudani SHavlicek JKorchemny DCerny EDudani SHavlicek JKorchemny D(2014)Introduction to Assertion-Based Formal VerificationSVA: The Power of Assertions in SystemVerilog10.1007/978-3-319-07139-8_20(453-466)Online publication date: 8-Jul-2014
https://doi.org/10.1007/978-3-319-07139-8_20
Mitra SBanerjee ADasgupta PKumar H(2013)Counterexample Ranking Using Mined InvariantsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.227662732:12(1978-1991)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1109/TCAD.2013.2276627
Mitra SBanerjee ADasgupta PRosenstiel WMacii E(2012)Formal methods for ranking counterexamples through assumption miningProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492937(911-916)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492937
Mitra SBanerjee ADasgupta P(2012)Formal methods for ranking counterexamples through assumption mining2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.1109/DATE.2012.6176627(911-916)Online publication date: Mar-2012
https://doi.org/10.1109/DATE.2012.6176627
Chen MQin XKoo HMishra PChen MQin XKoo HMishra P(2012)IntroductionSystem-Level Validation10.1007/978-1-4614-1359-2_1(1-17)Online publication date: 25-Sep-2012
https://doi.org/10.1007/978-1-4614-1359-2_1
Pulina LTacchella A(2011)NeVerAnnals of Mathematics and Artificial Intelligence10.1007/s10472-011-9243-062:3-4(403-425)Online publication date: 1-Jul-2011
https://dl.acm.org/doi/10.1007/s10472-011-9243-0
Claessen KRoorda J(2009)A Faithful Semantics for Generalised Symbolic Trajectory EvaluationLogical Methods in Computer Science10.2168/LMCS-5(2:1)20095:2Online publication date: 8-Apr-2009
https://doi.org/10.2168/LMCS-5(2:1)2009
Khasidashvili ZGavrielov GMelham T(2009)Assume-guarantee validation for STE properties within an SVA environment2009 Formal Methods in Computer-Aided Design10.1109/FMCAD.2009.5351133(108-115)Online publication date: Nov-2009
https://doi.org/10.1109/FMCAD.2009.5351133
Monsuez BVédrine FVallée N(2008)on the design of a formal debugger for system architectureProceedings of the 12th WSEAS international conference on Circuits10.5555/1576429.1576511(462-467)Online publication date: 22-Jul-2008
https://dl.acm.org/doi/10.5555/1576429.1576511
Beers RFix L(2008)Pre-RTL formal verificationProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391675(806-811)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391675
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Fifteen Years of Formal Property Verification in Intel

Formal verification of pipelined microprocessors by correspondence checking

Automatic formal verification of multithreaded pipelined microprocessors

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Fifteen Years of Formal Property Verification in Intel

Formal verification of pipelined microprocessors by correspondence checking

Automatic formal verification of multithreaded pipelined microprocessors

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