An approach to predicting dynamic power dissipation of coupled interconnect network in dynamic CMOS logic circuits

Abstract

In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with capacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capacitors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dynamic CMOS logic circuits.