Abstract
We present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Bi, G., Jones, E.V., 1989. A pipelined FFT processor for word-sequential data. IEEE Trans. Acoust. Speech Signal Process., 37(12):1982–1985. [doi:10.1109/29.45545]
Chang, Y.N., 2008. An efficient VLSI architecture for normal I/O order pipeline FFT design. IEEE Trans. Circ. Syst. II: Exp. Briefs, 55(12):1234–1238. [doi:10.1109/TCSII.2008.2008074]
Cheng, C., Parhi, K.K., 2007. High-throughput VLSI architecture for FFT computation. IEEE Trans. Circ. Syst. II: Exp. Briefs, 54(10):863–867. [doi:10.1109/TCSII.2007.901635]
Cortes, A., Velez, I., Sevillano, J.F., 2009. Radix rk FFTs: matricial representation and SDC/SDF pipeline implementation. IEEE Trans. Signal Process., 57(7):2824–2839. [doi:10.1109/TSP.2009.2016276]
Despain, A.M., 1974. Fourier transform computer using CORDIC iterations. IEEE Trans. Comput., c-23(10): 993–1001. [doi:10.1109/T-C.1974.223800]
Garrido, M., Parhi, K.K., Grajal, J., 2009. A pipelined FFT architecture for real-valued signals. IEEE Trans. Circ. Syst. I: Reg. Papers, 56(12):2634–2643. [doi:10.1109/TCSI.2009.2017125]
He, S., Torkelson, M., 1996. A New Approach to Pipeline FFT Processor. Proc. 10th Int. Symp. on Parallel Processing, p.766–770. [doi:10.1109/IPPS.1996.508145]
Lin, Y.W., Liu, H.Y., Lee, C.Y., 2005. A 1-GS/s FFT/IFFT processor for UWB applications. IEEE J. Sol.-State Circ., 40(8):1726–1735. [doi:10.1109/JSSC.2005.852007]
Oh, J.Y., Lim, M.S., 2005. Area and Power Efficient Pipeline FFT Algorithm. Proc. IEEE Workshop on Signal Processing System Design and Implementation, p.520–525. [doi:10.1109/SIPS.2005.1579923]
Rabiner, L.R., Gold, B., 1975. Theory and Application of Digital Signal Processing. Prentice-Hall, Inc., USA, p.604–609.
Sansaloni, T., Perez-Pascual, A., Torres, V., Valls, J., 2005. Efficient pipeline FFT processors for WLAN MIMO-OFDM systems. Electron. Lett., 41(19):1043–1044. [doi:10.1049/el:20052597]
Sung, T.Y., Hsin, H.C., Cheng, Y.P., 2010. Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems. Dig. Signal Process., 20(2):511–527. [doi:10.1016/j.dsp.2009.08.008]
Swartzlander, E.E., Young, W.K.W., Joseph, S.J., 1984. A radix 4 delay commutator for fast Fourier transforms processor implementation. IEEE J. Sol.-State Circ., 19(5):702–709. [doi:10.1109/JSSC.1984.1052211]
Wold, E.H., Despain, A.M., 1984. Pipeline and parallelpipeline FFT processors for VLSI implementation. IEEE Trans. Comput., c-33(5):414–426. [doi:10.1109/TC.1984.1676458]
Yeh, W.C., Jen, C.W., 2003. High-speed and low-power split-radix FFT. IEEE Trans. Signal Process., 51(3):864–874. [doi:10.1109/TSP.2002.806904]
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Liu, X., Yu, F. & Wang, Zk. A pipelined architecture for normal I/O order FFT. J. Zhejiang Univ. - Sci. C 12, 76–82 (2011). https://doi.org/10.1631/jzus.C1000234
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1631/jzus.C1000234