A Multi-Channel Data Simulator Based on the Time Unification System

Abstract

In satellite and airborne electro-optical tracking systems, there are numerous processing devices and complex data flows. To ensure the coordinated operation of the system, the multiple devices within the target system must operate under unified time control for data acquisition, computation, and output. This study introduces a multi-channel data simulator based on a time unification system. The complete simulation system includes the host computer, simulator, target system, and time reference generator. The simulator has programmable input and output interfaces for multi-channel protocols and has storage and real-time working modes. In the storage mode, the simulated data are pre-transmitted to the simulator’s storage and sent to the target system according to the time reference generator. The simulator simultaneously stores the target system results. In the real-time mode, the host computer generates simulated data based on the target system’s results and outputs the data through the simulator in real time. The main contribution of the simulator is that it achieves system-level closed-loop simulation and completes the functional and performance verification of the target system. Through experimental verification, it is found that the simulator can achieve 4.2 Gbps of simulated data transmission and 1.6 Gbps of data reception and storage, with a closed-loop delay of 39.9 µs.

1. Introduction

A simulator sends simulated data to a target system and receives its simulation results. A simulation system simulates the real working conditions of the target system and is widely used in various data and information processing systems, including remote sensing [1], global navigation satellite systems (GNSS) [2], radar systems [3], airborne photoelectric tracking systems, air-breathing hypersonic vehicles, etc. The real working environment simulation changes the data input of the next moment based on the processing results of the current moment. In the real environment, the input of the camera data of the target system will change according to the output of the turntable control, as shown in Figure 1a. Meanwhile, there are different heterogeneous processing devices in the target system, and the processing between different devices needs to be performed according to fixed beats and periods [4]. The unification of time is particularly important here [5,6]. Figure 1b shows the simulation working environment of the target system, including the time reference generator, the simulated data generator, the simulator, and the target system. The time reference generator generates a time reference and provides it to the simulator. The simulated data generator generates simulated data in real time based on the results of the target system. The simulator generates a unified time output, simulated output, and result input. The target system has multiple processing devices, and the simulated inputs of these devices include control signals and data streams. The target system’s inputs need to maintain a fixed delay relationship with the time reference input to satisfy the real processing timing of the processing devices, thus achieving time-unified simulation.

There are two main implementation methods for the simulator. One method is to send pre-set simulated data to the target system and store the results of the target system for subsequent analysis [7,8,9]. This method cannot generate dynamically changing simulated data based on the output of the target system and cannot achieve closed-loop simulation. The other method is to generate the simulated data required by the target system in real time and change the simulated data output at the next moment based on the output result of the simulation system [10,11,12,13,14]. The dynamic generation of high-speed simulated data requires a large number of calculations and will lead to differences in the data output time across different interfaces. This study proposes a multi-channel data simulator based on a time unification system, which can achieve the real-time closed-loop simulation of the data required for the target system simulation.

Simulated data from the source can be pre-generated and uniformly transmitted through the control of a host computer. Zhao et al. [7] achieved the simulation of data generated by space-borne sensors, with the simulated data stored using Flash and Compact Flash (CF) cards. However, the data output bandwidth was low due to the storage media, and it lacked synchronized input and result data input, making it impossible to achieve unified timing and closed-loop data simulation. Liu et al. [8] improved the data output bandwidth and the storage capacity of the simulated data by enhancing the storage method. Nevertheless, because the storage and transmission modules communicated via the PCI eXtensions for Instrumentation (PXIe) bus, the output of various interfaces was still asynchronous with the time reference. Wang et al. [9] utilized peripheral component interconnect express (PCIe), a Field-Programmable Gate Array (FPGA), and Double Data Rate Synchronous Dynamic Random Access Memory (DDR) to implement the buffering and transmission of simulated data, achieving closed-loop self-checking for data transmission and reception. However, due to the Direct Memory Access (DMA) transmission mechanism of PCIe, it lacks the capability for real-time high-speed data transmission and reception, thus failing to achieve real-time closed-loop simulation.

To achieve closed-loop simulation and emulate the real operating conditions of the target system, Liu et al. [10] and Meng et al. [11] implemented a multi-channel simulator that facilitates the conversion of data transmission protocols. However, the real-time simulated data generation is carried out on the simulator board. Due to its limited computational power, the simulator can only perform simple simulated data generation. Shi et al. [12] utilized Graphics Processing Unit (GPU) acceleration to generate simulator data, enabling the creation of complex simulated data. Nonetheless, due to the lack of input from the target system’s processing results, this system can only produce simulated data based on fixed configurations. Nannipieri et al. [13] and Dello Sterpaio et al. [14] proposed the SpaceWire and SpaceFibre test equipment based on the PXI industrial standard, which can be used to generate and store the data required by the payload equipment. However, their external trigger signals still require additional PXI peripheral modules for implementation, and their high-speed interfaces can only generate fixed test data packets, failing to produce simulated data based on real operating scenarios.

The main contribution of this study is that during the simulation process of the target system, the proposed data simulator can generate simulated data that are consistent with the real environment through a unified time reference, reducing the data differences between the simulation and real working conditions.

There are two innovative points highlighted in this study:

1. The proposed data simulator can receive Pulse-Per-Second (PPS) signals generated by the time reference generator. Through time synchronization, the simulator can achieve unified time with the target system, realizing data simulation under the real working conditions of the system.

2. The simulator can generate multiple channels of simulated data synchronized with the PPS signal, supporting various high-speed and low-speed interface protocols. It can send preset simulated data or generate simulated data in real time through the host computer, thereby achieving the closed-loop simulation verification of the target system.

This study introduces a multi-channel data simulator based on a time unification system. The complete simulation system includes the host computer, simulator, target system, and time reference generator. The simulator has two working modes: storage mode and real-time mode. The simulator has programmable input and output interfaces for multi-channel protocols, allowing for the simulation and storage of high-speed and low-speed data and control signals. In the storage mode, the simulated data on the host computer are transmitted to the simulator’s storage before simulation. Each channel of the interface sends data streams and control signals to the target system according to the time reference generator, while the simulator simultaneously stores the results output by the target system. In the real-time mode, the host computer generates simulated data and outputs them through the simulator in real time based on the results of the target system. Through experimental verification, it was found that the data simulator proposed in this study can achieve 4.2 Gbps of simulated data transmission and 1.6 Gbps of data reception and storage, with a closed-loop delay of 39.9 µs.

2. System Architecture of Simulator

Figure 2 depicts the system architecture of the proposed simulator, which comprises an FPGA controller, DDR, Serial Advanced Technology Attachment (SATA) solid-state storage, a PCIe×8 interface, a 10-gigabit Ethernet (10GbE) interface, a PPS interface, an input interface, and an output interface. The FPGA controller controls the various modules within the simulator and processes the input and output data. The DDR caches the input and output data, compensating for the timing differences between the SATA solid-state storage and the input/output interfaces. The PCIe interface transfers the simulated data, stored result data, and configuring parameters. The 10GbE interface transmits real-time output simulated data via the User Datagram Protocol (UDP) and simultaneously receives real-time result data. The PPS interface receives the PPS signal from the time reference generator, synchronizing the output timing of various output interfaces, and forwards it to the host computer via the UDP protocol for time synchronization. The input and output interfaces communicate with the target system, encompassing high-speed interfaces utilizing the TLK2711 serializer–deserializer and low-speed interfaces such as the Recommended Standard 422 (RS422), Controller Area Network (CAN), and Low-Voltage Differential Signaling (LVDS).

The simulator has two working modes: the storage mode and real-time mode.

In the storage mode, the simulator imports and exports simulated data and result data in large quantities with the host computer through the PCIe interface. The simulator can achieve high-speed offline data simulation and high-speed data recording and storage. By inputting the stored simulated data in advance, the simulator can output the data stably at a fixed frequency and cycle and store the result data output by the target system at the same time.

The storage mode of the simulator can achieve the synchronization of time between the simulator and the target system by inputting the time reference to simulate data transmission with a fixed period and delay. The simulator guarantees the fixed timing of the simulated output data through the two-level design of SATA solid-state storage and DDR. The SATA solid-state storage has a large capacity and can continuously simulate and output different data. Meanwhile, due to the storage’s non-volatile characteristics, the simulated data can still be saved after the simulator is powered off. The high-speed result data generated by the target system can also be stored in the SATA solid-state storage. The DDR ping-pong buffer design can avoid data loss due to the occupation of the SATA bus during storage. The PCIe interface can transmit data at high speed from the simulator to the host computer, saving time for the import and export of huge amounts of simulator data.

In real-time mode, the simulator and the host computer transmit data in real time through the 10GbE interface. The real-time mode can achieve the input and output of the real-time results and simulated data of the target system. The host computer calculates and outputs simulated data based on the real-time input result data and performs closed-loop simulation verification.

The real-time mode of the simulator can simulate the real working environment of the target system in a closed loop. The simulator forwards the results of the target system to the host computer, and the host computer outputs the simulated data of the next moment based on the results and the PPS. UDP network data transceiving through the 10GbE interface can effectively improve the real-time performance in terms of data output and reduce the closed-loop control delay.

The storage mode and real-time mode of the simulator work independently and in parallel. While in real-time mode, the simulator simultaneously stores the result data of the target system in the SATA solid-state storage. After the completion of the system’s closed-loop testing, users can export the data stored in the simulator to perform the subsequent analysis and processing of the test results.

3. The Design of the Time Unification

The clock of each device in the target system is generated by the internal oscillator, but the oscillator is highly sensitive to the environmental conditions, and time synchronization is required between different devices [15]. Time synchronization in the target system is usually achieved via the Global Positioning System (GPS) satellite timing method. A time reference generator with a GPS module can provide a 1 Hz PPS signal indicating the second signal [6]. The simulator needs to synchronize the data transmission times of multiple different protocol ports under the control of the PPS signal sent by the time reference generator in order to achieve the simulation of the real working environment of the target system. This section introduces the relevant design methods for the simulator with time synchronization.

3.1. The Time Unification Design in Storage Mode

The design of the time unification for the simulator in the storage working mode is shown in Figure 3. It mainly comprises a PPS control module, SATA solid-state storage module, SATA DMA module, DDR data buffer module, Data DMA module, Data First In First Out (FIFO) module, and output interface module. After completing the import of the simulated data into the SATA solid-state storage, the SATA DMA module finds the storage location of the simulated data based on the data index and transfers the simulated data to the DDR data buffer module in blocks when sending the simulated data to the target system. The SATA DMA module controls the Data DMA module to start the transfer between the DDR data buffer module and the Data FIFO module after completing the transfer of one data block. The Data FIFO module controls the sending of the data block according to the control of the PPS control module, following the configuration parameters with a fixed size, period, and delay. The Data FIFO module also sends a ready signal to the Data DMA module and SATA DMA module, thereby controlling the read speed of the Data DMA module and SATA DMA module.

The simulator can unify the timing of the output simulated data based on the PPS input in the storage mode and output the PPS to the target system, achieving the time unification system. The SATA solid-state storage can store a large amount of simulation data in a non-volatile manner, eliminating the need to reload the simulation data for each simulation in the same simulation scenario. The simulator is independent of the host computer’s operating system and achieves a stable simulated data output in the storage mode.

The simulator also has the function of storing the target system result data. It can store the high-speed result data output by the target system and enable subsequent simulation result analysis. The simulator communicates with the host computer through the PCIe interface for data transfer and control. The PCIe interface can realize high-speed data import and export.

3.2. The Time Unification Design in Real-Time Mode

The time unification design of the simulator in real-time mode is shown in Figure 4. It includes the PPS control module, host computer, 10GbE module, UDP packet decode module, Data FIFO module, and output interface module. The PPS control module sends the host computer signal of the time reference generator output to the host computer through a fixed UDP port. The host computer generates real-time simulated data based on the operating status of the target system, then it sends the multi-channel simulated data to the 10GbE module through different threads and multiple ports simultaneously. The UDP packet decode module parses the data packets from different ports, buffers the real-time output through the Data FIFO module, and sends it to the output interface module to the target system.

In the real-time mode, the host computer generates simulated data based on the received PPS data packet and sends the simulated data to the target system through different threads and ports. The target system sends the processing results back to the host computer through the simulator. The host computer can construct the next batch of simulated data to be sent based on the generated results, achieving closed-loop simulation. The PPS triggers the sending of UDP data packets and outputs them to the target system, achieving time synchronization between the host computer and the target system, which unifies the working rhythm and achieves the simulation of a real system.

4. The Design of the Multi-Working Mode

The simulator needs to adopt different operating modes for simulation testing depending on the phase of the whole system’s development process. In the early stages of the development of the target system, it is necessary to verify the system’s operational timing. The system’s operational timing can use the stored simulated data to for verification. In the later stages of the target system’s development, it is necessary to change the input data in real time based on the target system’s output. The simulator has a real-time operation mode, which enables it to perform the complete closed-loop verification of the system’s operation.

The simulator requires unified clocking and multi-channel interface processing. The use of a Field-Programmable Gate Array (FPGA) can effectively achieve the data synchronization and conversion of multiple ports. The FPGA structure of the simulator is shown in Figure 5. It includes DMA modules, PCIe control modules, PPS control modules, data FIFO modules, data switching modules, UDP protocol modules, and PPS, PCIe, 10GbE, DDR, SATA, input and output interface modules.

The DMA module handles data transfer between PCIe, SATA, data FIFO, and DDR, achieving the reading and writing of simulated and result data. The PCIe control module controls the DMA transfer according to the control commands from the host computer and configures the parameters of the PPS control module, enabling the sending of simulated data with variable cycles and delays. The PPS control module controls the data FIFO module’s data transmission timing and outputs the PPS signal to the target system and host computer. The data FIFO module sends simulated data in a fixed sequence under the control of the PPS control module. The data FIFO also buffers the received result data and waits for the DMA to write them into the SATA solid-state storage. The data switching module gates different data transmission and reception paths under different operating modes of the simulator. The UDP protocol module implements the ARP and UDP protocols, enabling UDP communication with the host computer, receiving and sending simulated and result data in real time, and sending fixed UDP data packets triggered by the PPS.

In storage mode, the host computer first uses the PCIe interface to ping-pong write the data to be transmitted to the DDR and then writes the data from the DDR to the SATA solid-state storage. When sending simulated data, the simulator reads the data from the SATA solid-state storage into the DDR and controls the period and delay of the DDR output to the high-speed output interface through the time reference signal input from the internal timer or external PPS interface, achieving a stable simulated data output.

When receiving result data, the input interface receives the high-speed result data generated by the target system; it then ping-pong buffers the result data into the DDR and writes the data from the DDR into the SATA solid-state storage. When the host computer needs to use the result data, the simulator reads the stored data from the SATA solid-state storage into the DDR and then uploads them to the host computer via the PCIe interface.

In real-time mode, the simulator first triggers the 10GbE interface to send fixed UDP packets to the host computer through the time reference signal input from the PPS interface. After receiving the UDP packets corresponding to the PPS, the host computer sends simulated data in parallel through different UDP ports. Upon receiving the data packets, the simulator parses the UDP packet information and then outputs the simulated data within the packets to the target system through the output interface. After the simulator input interface receives the result data from the target system, it packages the data into UDP packets and then sends them to the host computer through the 10GbE interface. The host computer generates the data to be simulated next in real time based on the results produced by the target system and sends them again when the PPS data packet arrives.

By reusing multiple modules, the simulator can achieve seamless switching between the storage mode and real-time mode without power interruption, thus meeting the simulation testing needs of different R&D stages of the target system.

5. Experimental Results

The simulator board card is shown in Figure 6. The FPGA uses xc7k325tffg900; the DDR cache uses 4 GB 800 M DDR3; the 10GbE interface uses an SFP optical port; the PCIe interface uses PCIe2.0 × 8; the SATA interface uses SATA3.0 × 2; the target system interface uses TLK2711, LVDS, RS422 and CAN; and the PPS interface uses an RS422 pulse input. The test environment is shown in Figure 7. The simulator is connected to the host computer through the PCIe interface and the 10GbE interface. The working status of the simulator can be obtained through the graphical user interface in the host computer.

The simulator uses a standard PCIe board card design, and the connection interface with the target system is located on both sides of the circuit board. The standard PCIe board card design can be conveniently integrated with different host computers to adapt to different simulation environments. The simulator has a 3 × 1.6 Gbps high-speed serial data output interface and a 1 × 1.6 Gbps high-speed serial input interface. It also has a 1 × 50 Mbps LVDS input and output, 1 × 1.2 Mbps synchronous RS422, 1 × 500 Kbps CAN, and 5 × 115,200 bps asynchronous RS422 input and output interfaces.

5.1. Storage Mode Loopback Test

The storage mode loopback test is shown in Figure 8. The simulator generates the PPS signal through the internal PPS generator and connects the output interface to the input interface. The host computer imports test data to the simulator through the PCIe interface and sends them synchronously according to the PPS to test the delay between the data and PPS. The host computer exports the received data through the PCIe interface after sending the data and compares the received data with the transmitted data to test their consistency.

The simulator proposed in this study can achieve a 4.2 Gbps and 1.6 Gbps high-speed data output and input capacity, as observed in actual tests. The received data obtained through loopback are found to be consistent with the transmitted data. The delay between the high-speed and low-speed interfaces and the time reference input is approximately 4.8 µs and 3.9 µs, as shown in Figure 9. The bandwidth and delay can meet the processing and synchronous receiving demands of the target system.

5.2. Real-Time Mode Loopback Test

The real-time mode loopback test is shown in Figure 10. The host computer sends the test data to the simulator through the 10GbE interface. The simulator outputs the test data through the output interface and realizes data loopback using external wiring. The received data are transmitted to the host computer through the 10GbE interface. The closed-loop delay of the simulator can be obtained by measuring the time difference between the sent and received data packets. Meanwhile, the received data are stored in the SATA solid-state storage. The received data are also uploaded to the host computer via PCIe for comparison with the transmitted data in order to test the consistency between the transmitted and received data.

The real-time mode loopback test uses the Wireshark network analysis tool on the host computer to analyze the transmitted UDP data packets. The simulator proposed in this study shows consistency among the received and transmitted data in real-time mode and can achieve an average closed-loop delay of 39.9 µs. The histogram shows the delay time distribution of 1037 test data packets with a delay range of 30–94 µs, and the delay time is generally distributed within 35–40 µs, as shown in Figure 11. It is found that 920 bytes is the largest number of packets transmitted in the target system. We capture the packets on the Windows operating system, which is not a real-time operating system. Due to the scheduling of backend tasks, there are occasionally more delays in parsing UDP data packets.

Table 1. Performance comparison of the simulator.

Item	Ours	Liu et al. [8]	Wang et al. [9]	Meng et al. [11]	Dello Sterpaio et al. [14]
High-speed output bandwidth	3 × 1.6 Gbps	6 × 1.6 Gbps	6 × 1.6 Gbps	2 × 300 Mbps	6 × 6.25 Gbps
High-speed input bandwidth	1 × 1.6 Gbps	-	-	8 × 400 Mbps	6 × 6.25 Gbps
Simulated data storage	2 × SATA3.0	NI-8261	DDR4	DDR4	-
Storage capacity	MAX 8 TB	MAX 2.9 TB	4 GB	4 GB	-
Closed-loop delay	39.9  µs	-	-	-	400 us
Host computer interface	PCIe + 10GbE	PXIe	PCIe	PXIe	PXIe
Time synchronization	Yes	No	No	No	No

compares the performance of the simulator proposed in this study with that of others. The simulators proposed by Liu et al. [8] and Wang et al. [9] can only output simulated data and cannot receive result data generated by the target system for closed-loop simulation. Additionally, they lack PPS input and cannot achieve time synchronization. The systems of Meng et al. [11] and Dello Sterpaio et al. [14] can generate simulated data based on the input data, but their computations are conducted on the FPGA, which only allows for simple data packaging and forwarding based on the data source and format, failing to achieve true data simulation. Moreover, since they do not have PPS input, they cannot send multiple data streams at a unified time, thus failing to achieve time synchronization.

The high-speed data simulator proposed in this study can meet the synchronized data transmission requirements of time-synchronized systems. The simulator features high-speed data reception ports to receive output data from the target system. Furthermore, the 10GbE Ethernet can transmit the simulated data generated by the host computer in real time, achieving closed-loop simulation.

6. Conclusions

In this study, a multi-channel data simulator based on a time unification system is proposed. The proposed simulator has programmable input and output interfaces for multi-channel protocols, allowing for the simulation and storage of high-speed and low-speed data and control signals. The proposed simulator has two working modes: storage mode and real-time mode. In the storage mode, the simulated data on the host computer are transmitted to the simulator’s storage before simulation. Each interface channel sends data streams and control signals to the target system according to the time reference generator, while the simulator simultaneously stores the results output by the target system. In the real-time mode, the host computer generates simulated data and outputs them through the simulator in real time, based on the results of the target system. The data simulator proposed in this study can achieve 4.2 Gbps of simulated data transmission and 1.6 Gbps of data reception and storage, with a closed-loop delay of 39.9 µs.

However, the host computer requires a certain amount of time to generate simulated data. In future work, in order to meet the needs of low-delay data generation, some of the simulated data generation steps of the host computer can be deployed to the simulator to reduce the delay in data generation. Moreover, using a real-time operating system such as RT-Linux in the host computer could reduce the effect of background tasks on the UDP packet parsing delay in the real-time mode.