WDC 65C816: Difference between revisions

* 8 (external)

* 16 (internal)}}

|pack1 = 40-pin [[Dual in-line package|DIP]]

|pack2 = 44-pin [[Plastic leaded chip carrier|PLCC]], others

|predecessor = {{plainlist|

* MOS 6502

* [[WDC 65C02]]}}

}}

 

The '''W65C816S''' (also '''65C816''' or '''65816''') is a 16-bit [[microprocessor]] (MPU) developed and sold by the [[Western Design Center]] (WDC). Introduced in 1983,<ref>[https://web.archive.org/web/20100206192831/http://processortimeline.info/proc1980.htm Chronology of Microprocessors (1980–1989)]</ref> the W65C816S is an enhanced version of the [[WDC 65C02]] [[8-bit computing|8-bit]] MPU, itself a [[CMOS]] enhancement of the venerable [[MOS Technology]] [[MOS Technology 6502|6502]] [[NMOS logic|NMOS]] MPU. The 65C816 is the CPU for the [[Apple IIGS]] and, in modified form, the [[Super Nintendo Entertainment System]].

 

 

At [[reset (computing)|reset]], the W65C816S starts in "emulation mode", meaning it substantially behaves as a 65C02. Thereafter, the W65C816S may be switched to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of [[backward compatibility]] with most 65C02 software. However, unlike the [[PDIP|PDIP40]] version of the 65C02, which is a [[pin-compatible]] replacement for its NMOS ancestor, the PDIP40 W65C816S is not pin-compatible with any other 6502 family MPU.

The same process also led to the 65C802, which was identical inside to the 65C816. Both were produced on the same fabrication lines and diverged only during the last metalization stages when the chip was being connected to the external pins. In the 65C802, those pins had the same layout as the original 6502, which allowed it to be used as a drop-in replacement while still allowing the 16-bit processing of the CPU to be used. However, as it used the original pinout it had only 16 addressing pins, and could therefore only access 64&nbsp;KB of external memory.{{sfn|Eyes|Lichty|1986|p=45}} Typically, when hardware manufacturers designed a project from the ground up, they used the 65C816 rather than the 65C802, resulting in the latter being withdrawn from production.

 

 

In the 1990s, both the 65C816 and 65C02 were converted to a fully [[static core]], which made it possible to completely stop the [[clock signal|processor's Ø2 clock]] without loss of register contents. This feature, along with the use of [[static RAM|asynchronous static RAM]], made it possible to produce designs that used minimal power when in a standby state.

 

 

[[File:WDC W65C802P 4 1.jpg|thumb|W65C802P]]

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The most obvious change to the 65C816 when running in native mode is the expansion of the various registers from 8-bit to 16-bit sizes. This enhancement affects the accumulator (<code>A</code>), the <code>X</code> and <code>Y</code> [[index register]]s, and the [[stack pointer]] (<code>SP</code>). It does not affect the [[program counter]] (<code>PC</code>), which has always been 16-bit.{{sfn|Eyes|Lichty|1986|p=46}}

 

 

In native mode operation, the accumulator and index registers may be set to 16- or 8-bit sizes at the programmer’s discretion by using the <code>REP</code> and <code>SEP</code> instructions to manipulate the <code>m</code> and <code>x</code> status register bits. This feature gives the programmer the ability to perform operations on either word- and byte-size data. As the accumulator and index register sizes are independently settable, it is possible, for example, to have the accumulator set to eight bits and the index registers set to 16 bits, giving the programmer the ability to manipulate individual bytes over a 64KB range without having to perform pointer arithmetic.

Internally, the 65c816 is a fully 16-bit design. The <code>m</code> and <code>x</code> bits in <code>SR</code> determine how the user registers (accumulator and index) appear to the rest of the system. Upon reset, the 65c816 starts in 6502 emulation mode, in which <code>m</code> and <code>x</code> are locked to <code>1</code>. Hence the registers are locked to eight-bit size. The most significant byte (MSB) of the accumulator (the <code>B</code>-accumulator) is not directly accessible but can be swapped with the least significant byte (LSB) of the accumulator (the <code>A</code>-accumulator) by using the <code>XBA</code> instruction. There is no corresponding operation for the index registers (<code>X</code> and <code>Y</code>), whose MSBs are locked at <code>$00</code>.

 

 

If the <code>x</code> bit in <code>SR</code> is cleared, both index registers will be set to 16 bits. If used to index an address, e.g., <code>LDA SOMEWHERE,X</code>, the 16-bit value in the index register will be added to the base address to form the effective address.

{{See also|MOS Technology 6502#Further reading|l1=List of books about 65xx microprocessor families}}

* ''[http://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf 65C816 Datasheet]''; Western Design Center; 55 pages; 2018.

 

==External links==