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In the 1990s, both the 65C816 and 65C02 were converted to a fully [[static core]], which made it possible to completely stop the [[clock signal|processor's Ø2 clock]] without loss of register contents. This feature, along with the use of [[static RAM|asynchronous static RAM]], made it possible to produce designs that used minimal power when in a standby state.
{{As of|April 2024}}, the W65C816S is available from WDC in 40 pin [[PDIP]], [[plastic leaded chip carrier|PLCC44]], or 44-pin [[Quad flat package#PQFP|TQFP]] packaging, as an [[microcontroller|MCU]] through the W65C265,<ref>{{Cite web |date=5 Jan 2021 |title=W65C265S 16-bit Microcontroller |url=https://www.westerndesigncenter.com/wdc/w65c265s-chip.php |url-status=live |archive-url=https://web.archive.org/web/20240402205917/https://www.westerndesigncenter.com/wdc/w65c265s-chip.php |archive-date=2 Apr 2024 |access-date=7 Apr 2024 |website=The Western Design Center, Inc.}}</ref> and as IP cores for [[Application-specific integrated circuit|ASIC]] integration<ref>{{Cite web |date=5 Jan 2021 |title=W65C816 8/16-bit Microprocessor |url=https://www.westerndesigncenter.com/wdc/w65c816s-core.php |url-status=live |archive-url=https://web.archive.org/web/20231115050721/https://www.westerndesigncenter.com/wdc/w65c816s-core.php |archive-date=15 Nov 2023 |access-date=7 Apr 2024 |website=The Western Design Center, Inc.}}</ref><ref>{{Cite web |date=5 Jan 2021 |title=W65C265S 8/16-bit Microcontroller |url=https://www.westerndesigncenter.com/wdc/w65c265s-core.php |url-status=live |archive-url=https://web.archive.org/web/20240407131630/https://www.westerndesigncenter.com/wdc/w65c265s-core.php |archive-date=7 Apr 2024 |access-date=7 Apr 2024 |website=The Western Design Center, Inc.}}</ref> (for example [[Winbond]]'s W55V9x series of TV [[Edutainment]] [[integrated circuit|IC]]s<ref>{{
[[File:WDC W65C802P 4 1.jpg|thumb|W65C802P]]
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The most obvious change to the 65C816 when running in native mode is the expansion of the various registers from 8-bit to 16-bit sizes. This enhancement affects the accumulator (<code>A</code>), the <code>X</code> and <code>Y</code> [[index register]]s, and the [[stack pointer]] (<code>SP</code>). It does not affect the [[program counter]] (<code>PC</code>), which has always been 16-bit.{{sfn|Eyes|Lichty|1986|p=46}}
When running in native mode, two bits in the status register change their meaning. In the original 6502, bits 4 and 5 were not used, although bit 4 is referred to as the break (<code>b</code>) flag. In native mode, bit 4 becomes the <code>x</code> flag and bit 5 becomes the <code>m</code> flag. These bits control whether or not the [[index register]]s (<code>x</code>) and
In native mode operation, the accumulator and index registers may be set to 16- or 8-bit sizes at the programmer’s discretion by using the <code>REP</code> and <code>SEP</code> instructions to manipulate the <code>m</code> and <code>x</code> status register bits. This feature gives the programmer the ability to perform operations on either word- and byte-size data. As the accumulator and index register sizes are independently settable, it is possible, for example, to have the accumulator set to eight bits and the index registers set to 16 bits, giving the programmer the ability to manipulate individual bytes over a 64KB range without having to perform pointer arithmetic.
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Internally, the 65c816 is a fully 16-bit design. The <code>m</code> and <code>x</code> bits in <code>SR</code> determine how the user registers (accumulator and index) appear to the rest of the system. Upon reset, the 65c816 starts in 6502 emulation mode, in which <code>m</code> and <code>x</code> are locked to <code>1</code>. Hence the registers are locked to eight-bit size. The most significant byte (MSB) of the accumulator (the <code>B</code>-accumulator) is not directly accessible but can be swapped with the least significant byte (LSB) of the accumulator (the <code>A</code>-accumulator) by using the <code>XBA</code> instruction. There is no corresponding operation for the index registers (<code>X</code> and <code>Y</code>), whose MSBs are locked at <code>$00</code>.
Upon being switched to native mode, the MSB of <code>X</code> and <code>Y</code> will be zero, and the <code>B</code>-accumulator will be unchanged. If the <code>m</code> bit in <code>SR</code> is cleared, the <code>B</code>-accumulator will be
If the <code>x</code> bit in <code>SR</code> is cleared, both index registers will be set to 16 bits. If used to index an address, e.g., <code>LDA SOMEWHERE,X</code>, the 16-bit value in the index register will be added to the base address to form the effective address.
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